mt9196asr1 Zarlink Semiconductor, mt9196asr1 Datasheet - Page 3

• Manufacturer Part Number: mt9196asr1
• Description: Fully Featured Digital Telephone Circuit With Built-in Filter/codec, Digital Gain Pads, Dtmf Generator, Tone Ringer, And Handset And Speakerphone Transducers
• Manufacturer: Zarlink Semiconductor

Overview
The functional block diagram of Figure 1 depicts the main operations performed by the MT9196 IDPC. Each of
these functional blocks will be described individually in the sections to follow. This overview will describe some of
the end-user features which may be implemented as a direct result of the level of integration found within the IDPC.
The main feature required of a digital telephone is to convert the digital Pulse Code Modulated (PCM) information,
being received by the telephone set, into an analog electrical signal. This signal is then applied to an appropriate
audio transducer such that the information is finally converted into intelligible acoustic energy. The same is true of
the reverse direction where acoustic energy is converted first into an electrical analog and then digitized (into PCM)
before being transmitted from the set. Along the way if the signals can be manipulated, either in the analog or the
digital domains, other features such as gain control and signal generation may be added. Finally, most electro-
acoustic transducers (loudspeakers) require a large amount of power if they are to develop an acoustic signal. The
inclusion of audio amplifiers to provide this power is required.
Pin Description (continued)
Pin #
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
CLOCKin Clock Input. The clock provided to this input is used by the internal phone functions. In ST-
HSPKR+ Non-Inverting Handset Speaker (Output). Output to the handset speaker (balanced).
HSPKR- Inverting Handset Speaker (Output). Output to the handset speaker (balanced).
STB/F0i Data Strobe/Frame Pulse (Input). For SSI mode this input determines the 8 bit timeslot
SPKR+
XSTL2
SPKR-
SS
AUX
Name
AUX
MIC+
V
D
V
D
SPKR Power Supply Rail for Speaker Driver. Nominally 0 Volts.
SSA
DD
out
in
out
in
Data Output. A tri-state digital output for 8 bit wide channel data being sent to the Layer 1
device. Data is shifted out via this pin concurrent with the rising edge of BCL during the
timeslot defined by STB, or according to standard ST-BUS timing.
Data Input. A digital input for 8 bit wide channel data received from the Layer 1 device. Data
is sampled on the falling edge of BCL during the timeslot defined by STB, or according to
standard ST-BUS timing. Input level is CMOS compatible.
used by the device for both transmit and receive data. This active high signal has a repetition
rate of 8 kHz. Standard frame pulse definitions apply in ST-BUS mode. CMOS level
compatible input.
BUS mode this is the C4i input. In SSI synchronous mode, this is the Bit Clock input. In SSI-
asynchronous mode this is an asynchronous 4 MHz Master Clock input.
Crystal Input (4.096 MHz). Used in conjunction with the CLOCKin pin to provide the master
clock signal via external crystal.
Positive Power Supply (Input). Nominally 5 volts.
Inverting Speaker (Output). Output to the speakerphone speaker (balanced).
Non-Inverting Speaker (Output). Output to the speakerphone speaker (balanced).
Auxiliary Port (Output). Access point to the D/A (analog) signals of the receive path as well
as to the various analog inputs.
Auxiliary Port (Input). An analog signal may be fed to the filter/codec transmit section and
various loopback paths via this pin. No external anti-aliasing is required.
Non-inverting on-hook answer back Microphone (Input). Microphone amplifier non-
inverting input pin.
Analog Ground (Input). Nominally 0 V.
Zarlink Semiconductor Inc.
MT9196
3
Description
Data Sheet