zl30100 Zarlink Semiconductor, zl30100 Datasheet - Page 13

• Manufacturer Part Number: zl30100
• Description: T1/e1 System Synchronizer
• Manufacturer: Zarlink Semiconductor

The delay value can be reset by setting the TIE corrector circuit Clear pin (TIE_CLR) low for at least 15 ns. This
results in a phase alignment between the input reference signal and the output clocks and frame pulses as shown
in Figure 17 on page 28 and Figure 18 on page 30. The speed of the phase alignment correction is limited to
61 Ps/s when BW_SEL=0. Convergence is always in the direction of least phase travel. In general the TIE
correction should not be exercised when Holdover mode is entered for short time periods. TIE_CLR can be kept
low continuously. In that case the output clocks will always be aligned with the selected input reference. This is
illustrated in Figure 7.
The Hitless Mode Switching (HMS) pin enables phase hitless returns from Freerun and Holdover modes to Normal
mode in a single reference operation. A logic low at the HMS input disables the TIE circuit updating the delay value
thereby forcing the output of the PLL to gradually move back to the original point before it went into Holdover mode.
(see Figure 8). This prevents accumulation of phase in network elements. A logic high (HMS=1) enables the TIE
circuit to update its delay value thereby preventing a large output phase movement after return to Normal mode.
This causes accumulation of phase in network elements. In both cases the PLL’s output can be aligned with the
input reference by setting TIE_CLR low. Regardless of the HMS pin state, reference switching in the ZL30100 is
always hitless unless TIE_CLR is kept low continuously.
REF1
REF1
REF0
REF0
Output
Clock
Output
Clock
TIE_CLR = 0
locked to REF1
locked to REF0
Figure 7 - Timing Diagram of Hitless Reference Switching
Zarlink Semiconductor Inc.
ZL30100
13
REF0
REF1
REF0
REF1
Output
Clock
Output
Clock
TIE_CLR = 1
locked to REF1
locked to REF0
Data Sheet