zl30100 Zarlink Semiconductor, zl30100 Datasheet - Page 17

• Manufacturer Part Number: zl30100
• Description: T1/e1 System Synchronizer
• Manufacturer: Zarlink Semiconductor

4.2
The loop filter settings can be selected through the BW_SEL pin, see Table 2.
4.3
The output clock and frame pulses of the frequency synthesizers are available in two groups controlled by the
OUT_SEL input. Table 3 lists the supported combinations of output clocks and frame pulses.
4.4
The ZL30100 has three possible manual modes of operation; Normal, Holdover and Freerun. These modes are
selected with the mode select pins MODE_SEL1 and MODE_SEL0 as is shown in Table 4. Transitioning from one
mode to the other is controlled by an external controller.
4.4.1
Freerun mode is typically used when an independent clock source is required, or immediately following system
power-up before network synchronization is achieved.
In Freerun mode, the ZL30100 provides timing and synchronization signals which are based on the master clock
frequency (supplied to OSCi pin) only, and are not synchronized to the reference input signals.
The Freerun accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a
output clock is required, the master clock must also be
page 23.
Loop Filter Selection
Output Clock and Frame Pulse Selection
Modes of Operation
Freerun Mode
BW_SEL
0
1
1
OUT_SEL
MODE_SEL1
0
1
0
0
1
1
Detected REF Frequency
8.192 MHz, 16.384 MHz
1.544 MHz, 2.048 MHz,
C1.5o, C2o, C16o, C32o, C65o
Table 3 - Clock and Frame Pulse Selection
MODE_SEL0
C1.5o, C2o, C4o, C8o, C16o
8 kHz
any
Generated Clocks
0
1
0
1
Table 2 - Loop Filter Settings
Table 4 - Operating Modes
Zarlink Semiconductor Inc.
ZL30100
r
17
32 ppm. See Applications - Section 6.2, “Master Clock“ on
Loop Filter Bandwidth
Normal (with automatic Holdover)
reserved (must not be used)
922 Hz
1.8 Hz
58 Hz
Holdover
Generated Frame Pulses
Freerun
Mode
F16o, F32o, F65o
F4o, F8o, F16o
Phase Slope Limiting
9.5 ms/s
9.5 ms/s
61 Ps/s
Data Sheet
r
32 ppm