zl30100 Zarlink Semiconductor, zl30100 Datasheet - Page 22

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zl30100

Manufacturer Part Number
zl30100
Description
T1/e1 System Synchronizer
Manufacturer
Zarlink Semiconductor
Datasheet

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The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output
to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and
frequency.
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. And better (smaller) phase slope performance (limiter) results in longer lock times.
6.0
This section contains ZL30100 application specific details for power supply decoupling, reset operation, clock and
crystal operation.
6.1
It is recommended to place a 100 nF decoupling capacitor close to the power and ground pairs as shown in Figure
12 to ensure optimal jitter performance.
in-lock phase distance
Power Supply Decoupling
Applications
3.3 V
Figure 12 - Recommended Power Supply Decoupling
100 nF
100 nF
100 nF
100 nF
100 nF
100 nF
100 nF
Zarlink Semiconductor Inc.
ZL30100
36 AV DD
29 AV
33 AGND
44 AV
41 AGND
45 AV
51 AGND
37 AV
34 GND
40 GND
25 V
23 GND
61 V
1 GND
22
DD
DD
DD
DD
DD
DD
ZL30100
AV
AV
V
CORE
CORE
V
CORE
GND 13
CORE
GND 1
14
35
12
2
100 nF
100 nF
100 nF
100 nF
1.8 V
Data Sheet

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