zl30102 Zarlink Semiconductor, zl30102 Datasheet - Page 21

• Manufacturer Part Number: zl30102
• Description: T1/e1 Stratum 4/4e Redundant System Clock Synchronizer For Ds1/e1 And H.110
• Manufacturer: Zarlink Semiconductor

4.4.3
Normal mode is typically used when a system clock source, synchronized to the network is required. In Normal
mode, the ZL30102 provides timing and frame synchronization signals, which are synchronized to one of three
reference inputs (REF0, REF1 or REF2). The input reference signal may have a nominal frequency of 8 kHz,
1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz. The frequency of the reference inputs are automatically
detected by the reference monitors.
When the ZL30102 comes out of RESET while Normal mode is selected by its MODE_SEL pins then it will initially
go into Holdover mode and generate clocks with the accuracy of its freerunning local oscillator (see Figure 11). If
the ZL30102 determines that its selected reference is disrupted (see Figure 3), it will remain in Holdover until the
selected reference is no longer disrupted or the external controller selects another reference that is not disrupted. If
the ZL30102 determines that its selected reference is not disrupted (see Figure 3) then the state machine will cause
the DPLL to recover from Holdover via one of two paths depending on the logic level at the HMS pin. If HMS=0 then
the ZL30102 will transition directly to Normal mode and it will align its output signals with its selected input
reference (see Figure 9). If HMS=1 then the ZL30102 will transition to Normal mode via the TIE correction state and
the phase difference between the output signals and the selected input reference will be maintained.
When the ZL30102 is operating in Normal mode, if it determines that its selected reference is disrupted (Figure 3)
then its state machine will cause it to automatically go to Holdover mode. When the ZL30102 determines that its
selected reference is not disrupted then the state machine will cause the DPLL to recover from Holdover via one of
two paths depending on the logic level at the HMS pin (see Figure 11). If HMS=0 then the ZL30102 will transition
directly to Normal mode and it will align its output signals with its input reference (see Figure 9). If HMS=1 then the
ZL30102 will transition to Normal mode via the TIE correction state and the phase difference between the output
signals and the input reference will be maintained.
If the reference selection changes because the value of the REF_SEL1:0 pins changes or because the reference
selection state machine selected a different reference input, the ZL30102 goes into Holdover mode and returns to
Normal mode through the TIE correction state regardless of the logic value on HMS pin.
ZL30102 provides a fast lock pin (FASTLOCK), which, when set high enables the PLL to lock to an incoming
reference within approximately 1 s.
REF_DIS=1: Current selected reference disrupted (see Figure 3). REF_DIS is an internal signal.
REF_CH= 1: Reference change, a transition in the reference selection (see Figure 13) or a change in the
REF_SEL pins. REF_CH is an internal signal.
Normal Mode
RST
(HOLDOVER=1)
REF_CH=0 and
HMS=0
REF_DIS=0 and
Figure 11 - Mode Switching in Normal Mode
Holdover
Zarlink Semiconductor Inc.
(REF_DIS=0 and HMS=1) or
ZL30102
REF_DIS=1
(HOLDOVER=0)
21
REF_DIS=1
REF_DIS=0
REF_CH=1
Normal
REF_CH=1
(HOLDOVER=1)
TIE Correction
Data Sheet