zl30102 Zarlink Semiconductor, zl30102 Datasheet - Page 32

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zl30102

Manufacturer Part Number
zl30102
Description
T1/e1 Stratum 4/4e Redundant System Clock Synchronizer For Ds1/e1 And H.110
Manufacturer
Zarlink Semiconductor
Datasheet

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6.0
This section contains ZL30102 application specific details for power supply decoupling, reset operation, clock and
crystal operation.
6.1
Jitter levels on the ZL30102 output clocks may increase if the device is exposed to excessive noise on its power
pins. For optimal jitter performance, the ZL30102 device should be isolated from noise on power planes connected
to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note
ZLAN-178.
6.2
The ZL30102 can use either a clock or crystal as the master timing source. Zarlink application note ZLAN-68 lists a
number of applicable oscillators and crystals that can be used with the ZL30102.
6.2.1
When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency,
frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise.
The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30102, and the OSCo
output should be left open as shown in Figure 19.
Power Supply Decoupling
Master Clock
Applications
Clock Oscillator
1
2
3
4
Table 7 - Typical Clock Oscillator Specification
Frequency
Tolerance
Rise & fall time
Duty cycle
ZL30102
Figure 19 - Clock Oscillator Circuit
OSCo
Zarlink Semiconductor Inc.
OSCi
No Connection
ZL30102
32
20 MHz OUT
20 MHz
as required
< 10 ns
40% to 60%
+3.3 V
+3.3 V
GND
0.1 µF
Data Sheet

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