zl30109 Zarlink Semiconductor, zl30109 Datasheet - Page 10

• Manufacturer Part Number: zl30109
• Description: Ds1/e1 System Synchronizer With 19.44 Mhz Output
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
3.0
The ZL30109 is a DS1/E1 System Synchronizer providing timing (clock) and synchronization (frame) signals to
interface circuits for DS1 and E1 Primary Rate Digital Transmission links and OC-3/STM-1 links, as well as a
19.44 MHz output for SDH line card applications. Figure 1 is a functional block diagram which is described in the
following sections.
3.1
The ZL30109 accepts two simultaneous reference input signals and operates on their rising edges. One of them,
the primary reference (REF0) or the secondary reference (REF1) signal can be selected as input to the TIE
corrector circuit based on the reference selection (REF_SEL) input.
3.2
The input references are monitored by two independent reference monitor blocks, one for each reference. The
block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is
detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of
the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper
operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be
observed.
Pin #
53
54
55
56
57
58
59
60
61
62
63
64
Reference Select Multiplexer (MUX)
Reference Monitor
Functional Description
OOR_SEL
REF_SEL
TIE_CLR
BW_SEL
Name
REF0
REF1
V
NC
NC
NC
NC
IC
DD
Reference Select (Input). This input selects the input reference that is used for
synchronization, see Table 5 on page 20. This pin is internally pulled down to GND.
No internal bonding Connection. Leave unconnected.
Reference (Input). This is one of two (REF0, REF1) input reference sources used for
synchronization. One of seven possible frequencies may be used: 2 kHz, 8 kHz,
1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz, or 19.44 MHz. This pin is internally
pulled down to GND.
No internal bonding Connection. Leave unconnected.
Reference (Input). See REF0 pin description.
No internal bonding Connection. Leave unconnected.
Internal Connection. Connect this pin to ground.
Out Of Range Selection (Input). This pin selects the out of range reference rejection
limits, see Table 1 on page 17.
Positive Supply Voltage. +3.3 V
No internal bonding Connection. Leave unconnected.
TIE Corrector Circuit Reset (Input). A logic low at this input resets the Time Interval
Error (TIE) correction circuit resulting in a realignment of the input phase with the output
phase.
Filter Bandwidth Selection (Input). This pin selects the bandwidth of the DPLL loop
filter, see Table 2 on page 18. Set continuously high to track jitter on the input reference
closely or set temporarily high to allow the ZL30109 to quickly lock to the input reference.
Zarlink Semiconductor Inc.
ZL30109
10
DC
nominal.
Description
Data Sheet