zl30109 Zarlink Semiconductor, zl30109 Datasheet - Page 21

• Manufacturer Part Number: zl30109
• Description: Ds1/e1 System Synchronizer With 19.44 Mhz Output
• Manufacturer: Zarlink Semiconductor

5.0
The following are some PLL performance indicators and their corresponding definitions.
5.1
Timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander
is defined as the low-frequency variation of the clock edges from their ideal positions in time. High and low
frequency variation imply phase oscillation frequencies relative to some demarcation frequency. (Often 10 Hz or
20 Hz for DS1 or E1, higher for SONET/SDH clocks.) Jitter parameters given in this data sheet are total timing jitter
numbers, not cycle-to-cycle jitter.
5.2
Jitter generation is the measure of the jitter produced by the PLL and is measured at its output. It is measured by
applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Jitter generation
may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by
measuring the output jitter of the device. Jitter generation is usually measured with various bandlimiting filters
depending on the applicable standards.
5.3
Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the
presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied
jitter magnitude and jitter frequency depends on the applicable standards.
5.4
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
For the Zarlink digital PLLs two internal elements determine the jitter attenuation; the internal low pass loop filter
and the phase slope limiter. The phase slope limiter limits the output phase slope to, for example, 61 µs/s.
Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the
maximum output phase slope will be limited (i.e., attenuated).
Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for
large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter
signals (for example 75% of the specified maximum tolerable input jitter).
Jitter
Jitter Generation (Intrinsic Jitter)
Jitter Tolerance
Jitter Transfer
Measures of Performance
Note: LOCK pin behaviour depends on phase and frequency offset of REF1.
REF_SEL
LOCK
Figure 11 - Reference Switching in Normal Mode
REF0
Zarlink Semiconductor Inc.
REF1
ZL30109
21
Lock Time
Data Sheet