mt9079apr1 Zarlink Semiconductor, mt9079apr1 Datasheet - Page 5
![no-image](/images/manufacturer_photos/0/7/727/zarlink_semiconductor_sml.jpg)
mt9079apr1
Manufacturer Part Number
mt9079apr1
Description
Advanced Controller For E1
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT9079APR1.pdf
(74 pages)
Pin Description (continued)
Note: 1.All inputs are CMOS with TTL compatible logic levels.
Note: 2.All outputs are CMOS and are compatible with both TTL and CMOS logic levels.
Note: 3.See AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels for input and output voltage thresholds.
DIP
29
30
31
32
33
34
35
36
37
38
39
40
-
Pin #
PLCC
32
33
34
35
36
37
38
39
40
41
42
43
44
QFP
26
27
28
29
30
31
32
33
34
35
36
37
38
CSTo1 Control ST-BUS Output One (Output): A 2.048 Mbit/s serial status stream which
Name
CSTi2 Control ST-BUS Input Two (Input): A 2.048 Mbit/s ST-BUS control stream which
RxMF
TxMF
E8Ko
DSTi
TAIS
TxB
TxA
S/P
V
NC
IC
SS
Extracted 8 kHz Clock (Output): An 8 kHz signal generated by dividing the
extracted 2.048 MHz clock (E2i) by 256 and aligning it with the received PCM 30
frame. The 8 kHz signal can be used to synchronize the system clock with the
extracted 2.048 MHz clock. E8Ko is high when 8KSEL=0. See Figure 27.
Data ST-BUS (Input). A 2.048 Mbit/s serial stream which contains the 30 PCM or
data channels to be transmitted on the PCM 30 line. See Figure 4a.
Receive Multiframe Boundary (Output): An output pulse delimiting the received
multiframe boundary. The next frame output on the data stream (DSTo) is basic frame
zero on the PCM 30 link. This receive multiframe signal can be related to either the
receive CRC multiframe (MFSEL=1) or the receive signalling multiframe (MFSEL=0).
See Figures 25 and 26.
Transmit Multiframe Boundary (Input): This input is used to set the channel
associated and CRC transmit multiframe boundary. The device will generate its own
multiframe if this pin is held high. This input is pulled high in most applications. See
Figures 24 to 26.
Serial/Parallel (Input): High - serial controller port or ST-BUS operation.
Low - parallel processor port operation.
Negative Power Supply (Input): Ground.
contains the 30 (ABCDXXXX) transmit signalling nibbles when RPSIG=0.
RPSIG=1 this pin has no function. Only the most significant nibbles of each ST-BUS
timeslot are valid. See Figure 4c.
No Connection.
provides the 30 (ABCDABCD) receive signalling nibbles. See Tables 15 - 17.
Transmit Alarm Indication Signal (Input): High - TxA and TxB will transmit data
normally. Low - TxA and TxB transmits an AIS (all ones signal).
Transmit B (Output): A split phase unipolar signal suitable for use with TxA, an
external line driver and a transformer to construct a bipolar PCM 30 line signal. This
output can also transmit RZ and NRZ bipolar signals. See Figures 28 and 30.
Transmit A (Output):A split phase unipolar signal suitable for use with TxB, an
external line driver and a transformer to construct a bipolar PCM 30 line signal. This
output can also transmit RZ and NRZ bipolar signals. See Figures 28 and 30.
Internal Connection (Input): Connect to ground for normal operation.
Zarlink Semiconductor Inc.
MT9079
Description (see notes 1, 2 and 3)
5
Data Sheet
When