mt9079apr1 Zarlink Semiconductor, mt9079apr1 Datasheet - Page 56

• Manufacturer Part Number: mt9079apr1
• Description: Advanced Controller For E1
• Manufacturer: Zarlink Semiconductor

It should be noted that the DS signal of the MC68302 must be inverted to interface to the MT8980D. Also, DTACK
must be connected to the MT8980D DTA and pulled-up with a 909 ohms resistor.
G.703 and G.704 Operation
The MT9079 supports three basic G.703 2.048 Mbit/sec. configurations. The first is normal framing where
receive G.703 data is clocked onto the ST-BUS based on addresses which are referenced to the receive G.704
Frame Alignment Signal (FAS). On the transmit side the ST-BUS channel zero (and optionally channel 16) are
replaced by G.704 framer generated signals. The second is transparent mode, which is described in the next
application section.
The third configuration is where the MT9079 passes G.703 data on to another framing device such as an HDLC
controller. That is, the receive data is clocked onto the ST-BUS without any reference to a G.704 FAS and
transmit data is not altered by the framer. This is described in Table 67. In this configuration the control and
status functions that are associated with individual channels will not work predictably. Other functions such as
HDB3 encoding, interrupts, loopbacks, RSLIP, LOSS, AISS, AUXP and the BPV error counter work normally.
The control bits CRCM, MODE and RxG704 are cleared by either a software or hardware reset.
The MT9079 Transparent Mode
Figure 15 illustrates an application in which the MT9079 transparent mode can be used. That is, a digital cross-
connect multiplexer that switches complete PCM 30 trunks and does not require time slot switching. It should be
noted that any MT9079 devices that transport time slot switched data must operate in termination mode otherwise,
the CRC-4 remainder will be in error.
In transparent mode the complete PCM 30 data stream will pass through the MT9079 except for the data link (S
of the NFAS - 4kbit/sec. maintenance channel). The CRC-4 remainder will not be generated by the transmit section
of the MT9079, but the CRC-4 remainder bits received on DSTi will be modified to reflect the new data link bits. This
has the advantage that any CRC-4 errors that occur on the receive span will not be masked on the transmit span
even though the maintenance channel has been modified. See Table 67.
The RxMF signal must be associated with the CRC-4 multiframe (control bit MFSEL = 1), and RxMF of the receive
trunk must be connected to TxMF of the transmit trunk. The data delay time (DSTo to DSTi) and the TxMF to RxMF
delay must be equal. Therefore, a m + 1 frame delay circuit is added to the TxMF to RxMF connection (where: m is
the delay in basic frames through the Digital Cross-Connect Matrix).
C4
Figure 14 - Common Channel Signalling Control (Time Slot 16) through the MC68302
MT8980D
C4i
CSTo
STon
STin
DTA
MT8980 P Interface
909
+5V
Address
Control
100
Data
&
MC68302
Zarlink Semiconductor Inc.
MT9079
MT9079 P Interface
100
56
C2
DSTi
DSTo
MT9079
C4i/C2i
TxA
TxB
RxA
RxB
E2i
To Trunk Interface
Data Sheet
a4