zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 78
zl50118gag2
Manufacturer Part Number
zl50118gag2
Description
32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50118GAG2.pdf
(94 pages)
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Part Number:
ZL50118GAG2
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12.6.2
RXCLK period
RXCLK high wide time
RXCLK low wide time
RXCLK rise time
RXCLK fall time
RXD[3:0] setup time (RXCLK
rising edge)
RXD[3:0] hold time (RXCLK
rising edge)
RXDV input setup time
(RXCLK rising edge)
RXDV input hold time (RXCLK
rising edge)
RXER input setup time (RXCL
edge)
RXER input hold time (RXCLK
rising edge)
RXD[3:0]
MII Receive Timing
RXCLK
Parameter
RXDV
RXER
Table 31 - MII Receive Timing - 100 Mbps
Symbol
t
t
t
t
t
t
t
t
t
DVS
DVH
ERS
ERH
Figure 33 - MII Receive Timing Diagram
t
t
CC
CH
CR
DH
CL
CF
DS
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
t
t
DVS
DS
Min.
14
14
10
10
10
5
5
5
-
-
-
t
DH
78
t
CC
100 Mbps
t
Typ.
ERS
40
20
20
-
-
-
-
-
-
-
-
t
ERH
Max.
26
26
5
5
-
-
-
-
-
-
-
t
CLO
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CHI
t
DVH
Data Sheet
Notes
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