zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 9
zl50118gag2
Manufacturer Part Number
zl50118gag2
Description
32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50118GAG2.pdf
(94 pages)
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The following table captures the changes from the July 2005 issue.
The following table captures the changes from the April 2005 issue.
The following table captures the changes from the January 2005 issue.
The following table captures the changes from the November 2004 issue.
39, 40
Page
Page
Page
Page
50
85
85
39
Section 4.5 and Section 4.6.2
Section 6.3
Figure 42
Figure 43
Section 4.6.1
Item
Item
Item
Item
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
Added external pull-up/pull-down resistor
recommendations for SYSTEM_RST,
SYSTEM_DEBUG, JTAG_TRST, JTAG_TCK.
Added Section 6.3 SYSTEM_CLK Considerations.
Clarified data sheet to indicate ZL5011x supports clock
recovery in both synchronous and asynchronous modes
of operation.
Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to
conform with default MPC8260. Polarity of CPU_DREQ
and CPU_SDACK remains programmable through API.
Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to
conform with default MPC8260. Polarity of CPU_DREQ
and CPU_SDACK remains programmable through API.
Added 5 kohm pulldown recommendation to GPIO
signals.
9
Change
Change
Change
Change
Data Sheet
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