zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 80
zl50118gag2
Manufacturer Part Number
zl50118gag2
Description
32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50118GAG2.pdf
(94 pages)
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Part Number:
ZL50118GAG2
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12.6.4
RXCLK period
RXCLK high wide time
RXCLK low wide time
RXCLK rise time
RXCLK fall time
RXD[7:0] setup time (RXCLK
rising edge)
RXD[7:0] hold time (RXCLK
rising edge)
RXDV setup time (RXCLK
rising edge)
RXDV hold time (RXCLK
rising edge)
RXER setup time (RXCLK
rising edge)
RXER hold time (RXCLK
rising edge)
RXD[7:0]
GMII Receive Timing
RXCLK
Parameter
RXDV
RXER
Table 33 - GMII Receive Timing - 1000 Mbps
Symbol
Figure 35 - GMII Receive Timing Diagram
t
t
t
t
t
t
t
t
t
DVS
DVH
ERS
ERH
t
t
CC
CH
CR
DH
CL
CF
DS
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
t
t
DVS
DS
Min.
7.5
2.5
2.5
2
1
2
1
2
1
-
-
t
DH
80
t
CC
1000 Mbps
t
Typ.
ERS
-
-
-
-
-
-
-
-
-
-
-
t
ERH
Max.
8.5
1
1
-
-
-
-
-
-
-
-
t
CLO
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CHI
t
DVH
Data Sheet
Notes
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