zl50404 Zarlink Semiconductor, zl50404 Datasheet - Page 2
zl50404
Manufacturer Part Number
zl50404
Description
Lightly Managed/unmanaged 5-port 10/100m Ethernet Switch
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50404.pdf
(121 pages)
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Per queue traffic shaper on uplink port
Packet Filtering and Port Security
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QoS Support
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Supports per-system option to enable flow control for best effort frames even on QoS enabled ports
Classification based on:
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The precedence of the above classifications is programmable
Supports IEEE 802.3ad link aggregation
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Supports module hot swap on all ports
MIB Statistics counters for all ports
Full Duplex Ethernet IEEE 802.3x Flow Control
Backpressure flow control for Half Duplex ports
Hardware auto-negotiation through MII management interface (MDIO) for Ethernet ports
Built-in reset logic triggered by system malfunction
Built-In Self Test for internal SRAM
IEEE-1149.1 (JTAG) test port
Static address filtering for source and/or destination MAC
Static MAC address not subject to aging
Secure mode freezes MAC address learning (each port may independently use this mode)
Supports port authentication (IEEE 802.1x)
Supports IEEE 802.1p/Q Quality of Service with 2 transmission priority queues (4 for uplink port), with
strict priority and/or WFQ service disciplines
Provides 2 levels of dropping precedence with WRED mechanism
User controls the WRED thresholds.
Buffer management: per class and per port buffer reservations
Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID
Port based priority
VLAN Priority field in VLAN tagged frame
DS/TOS field in IP packet
UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range
8 groups of up to 4 ports per group
Supports load sharing among trunked ports based on:
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Source port
Source and/or destination MAC address
Zarlink Semiconductor Inc.
ZL50404
2
Data Sheet
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