zl50404 Zarlink Semiconductor, zl50404 Datasheet - Page 25

• Manufacturer Part Number: zl50404
• Description: Lightly Managed/unmanaged 5-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

Specifically, there are the following types of control frames generated by the CPU and sent to the ZL50404:
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Note: Memory read and write requests by the CPU may include all internal memories which include statistic
counters, MAC address control link table and the 2Mbit (256KB) memory block.
In addition, the following types of Control frames are generated by the ZL50404 and sent to the CPU:
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The format of the Control Frame is described in the Processor Interface application note, ZLAN-26.
Although there is the ability to Tx/Rx Control Frames via the serial interface in lightly managed mode, the ZL50404
is not meant to be used in a fully managed system. The speed of the serial interface limits management capability.
For example, if the system is trying to manage the MAC learning/deletion, it would require a faster interface
between the CPU and the ZL50404, such as the 8/16-bit interface found on the managed device.
3.2
The I²C interface serves the function of configuring the ZL50404 at boot time. The master is the ZL50404, and the
slave is the EEPROM memory.
The I²C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the
control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and
bidirectional, at 50 Kbps. Data transfer is performed between master and slave IC using a request /
acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. Figure
4 depicts the data transfer format. The slave address is the memory address of the EEPROM. Refer to “ZL50404
Register Description” on page 52 for I²C address for each register.
3.2.1
Generated by the master (in our case, the ZL50404). The bus is considered to be busy after the Start condition is
generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line.
Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High
period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I²C bus is
free, both lines are High.
Memory read request
Memory write request
Learn Unicast MAC address
Delete Unicast MAC address
Search Unicast MAC address
Learn Multicast MAC address
Delete Multicast MAC address
Search Multicast MAC address
Interrupt CPU when statistics counter rolls over
Response to memory read request from CPU
Learn Unicast MAC address
Delete Unicast MAC address
Delete Multicast MAC address
Response to search Unicast MAC address request from CPU
Response to search Multicast MAC address request from CPU
START
I
2
C Interface
Start Condition
SLAVE ADDRESS
Figure 4 - Data Transfer Format for I²C Interface
R/W
ACK
Zarlink Semiconductor Inc.
DATA 1 (8bits)
ZL50404
25
ACK
DATA 2
ACK
DATA M
ACK
Data Sheet
STOP