zl50404 Zarlink Semiconductor, zl50404 Datasheet - Page 55
zl50404
Manufacturer Part Number
zl50404
Description
Lightly Managed/unmanaged 5-port 10/100m Ethernet Switch
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50404.pdf
(121 pages)
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USER_PORTn_LOW
USER_PORTn_HIGH
USER_PORT1:0_
PRIORITY
USER_PORT3:2_
PRIORITY
USER_PORT5:4_
PRIORITY
USER_PORT7:6_
PRI ORITY
USER_PORT_
ENABLE[7:0]
USER_PORT_
FORCE_DISCARD[7:0]
RLOWL
RLOWH
RHIGHL
RHIGHH
RPRIORITY
6. MISC Configuration Register
MII_OP0
MII_OP1
FEN
MIIC0
MIIC1
MIIC2
MIIC3
MIID0
MIID1
USD
Register
User Define Logical Port n
Low
User Define Logical Port n
High
User Define Logic Port 0
and 1 Priority
User Define Logic Port 2
and 3 Priority
User Define Logic Port 4
and 5 Priority
User Define Logic Port 6
and 7 Priority
User Define Logic Port 0 To
7 Enable
User Define Logic Port 0 To
7 Force Discard Enable
User Define Range Low Bit
[7:0]
User Define Range Low Bit
[15:8]
User Define Range High Bit
[7:0]
User Define Range High Bit
[15:8]
User Define Range Priority
MII Register Option 0
MII Register Option 1
Feature Registers
MII Command Register 0
MII Command Register 1
MII Command Register 2
MII Command Register 3
MII Data Register 0
MII Data Register 1
One micro second divider
Table 12 - Register Description (continued)
Description
Zarlink Semiconductor Inc.
ZL50404
55
CPU Addr
570+2n
571+2n
(Hex)
5A0
5A1
5A2
5A3
5A4
602
603
604
605
606
609
590
591
592
593
594
595
600
601
607
608
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
09A+n
092+n
(Hex)
Addr
0BC
0BD
0AE
0AF
0BE
0A2
0A3
0A4
0A5
0A6
0A7
0B0
0B1
0B2
I²C
NA
NA
NA
NA
NA
NA
NA
Default
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
010
000
000
000
000
000
NA
NA
Data Sheet
(n=0..7)
Notes
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