zl50409 Zarlink Semiconductor, zl50409 Datasheet - Page 109

• Manufacturer Part Number: zl50409
• Description: Managed 9-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.9.8
I²C Address h0CA, CPU Address 869
Accessed by CPU and I²C (R/W)
Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop
or flow control (Default 0x12)
12.3.9.9
Accessed by CPU and I²C (R/W)
•
•
Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue
size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the
queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED.
12.3.9.10
I²C Address 07A-087, CPU Address:h882-88F
Accessed by CPU and I²C (R/W)
Same as QOSC00, QOSC01
12.3.9.11
Accessed by CPU and I
•
•
•
•
•
•
Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue
size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the
queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED.
12.3.9.12
Accessed by CPU and I²C (R/W)
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•
•
•
•
•
Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue
size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the
queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED.
QOSC00 – BYTE_L1 (I²C Address h078, CPU Address 880)
QOSC01 – BYTE_L2 (I²C Address h079, CPU Address 881)
QOSC16 – BYTE_L11 Level 1 for queue 1 (I
QOSC17 – BYTE_L21 Level 2 for queue 1 (I
QOSC18 – BYTE_L12 Level 1 for queue 2 (I
QOSC19 – BYTE_L22 Level 2 for queue 2 (I
QOSC20 – BYTE_L13 Level 1 for queue 3 (I
QOSC21 – BYTE_L23 Level 2 for queue 3 (I
QOSC22 – BYTE_L11 Level 1 for queue 1 (I²C Address h08E, CPU Address 896)
QOSC23 – BYTE_L21 Level 2 for queue 1 (I²C Address h08F, CPU Address 897)
QOSC24 – BYTE_L12 Level 1 for queue 2 (CPU Address 898)
QOSC25 – BYTE_L22 Level 2 for queue 2 (CPU Address 899)
QOSC26 – BYTE_L13 Level 1 for queue 3 (CPU Address 89A)
QOSC27 – BYTE_L23 Level 2 for queue 3 (CPU Address 89B)
PTHG – Port MMAC Threshold
QOSC00, QOSC01 - Classes Byte Limit port 0
QOSC16 - QOSC21 - Classes Byte Limit CPU port
QOSC22 - QOSC27 - Classes Byte Limit MMAC port
QOSC02, QOSC15 - Classes Byte Limit port 1-7
2
C (R/W):
Zarlink Semiconductor Inc.
2
2
2
2
2
2
C Address h088, CPU Address 890)
C Address h089, CPU Address 891)
C Address h08A, CPU Address 892)
C Address h08B, CPU Address 893)
C Address h08C, CPU Address 894)
C Address h08D, CPU Address 895)
ZL50409
109
Data Sheet