zl50409 Zarlink Semiconductor, zl50409 Datasheet - Page 119

• Manufacturer Part Number: zl50409
• Description: Managed 9-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.11.2
CPU Address: hF01
Accessed by CPU (RO)
12.3.11.3
CPU Address: hF02
Accessed by CPU (RO)
12.3.11.4
CPU Address:hF03
Accessed by CPU (R/W)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bits [5:4]:
Bits [7:6]:
Bits [6:0]
Bit [7]
Bits [4:0]:
Bits [7:5]:
DCR - Device Status and Signature Register
DCR1 - Device Status Register 1
DPST – Device Port Status Register
1: Busy writing configuration to I²C
0: Not busy (not writing configuration to I²C)
1: Busy reading configuration from I²C
0: Not busy (not reading configuration from I²C)
1: BIST in progress
0: BIST not running
1: RAM Error
0: RAM OK
Device Signature
10: ZL50409 device
Revision
00: Initial Silicon
01: Second Silicon
Reserved
Chip initialization completed
Read back index register. This is used for selecting what to read back from
DTST. (Default 00)
Reserved
-
-
-
-
-
-
-
-
-
-
5’b00000 - Port 0 Operating mode and Negotiation status
5’b00001 - Port 1 Operating mode and Negotiation status
5’b00010 - Port 2 Operating mode and Negotiation status
5’b00011 - Port 3 Operating mode and Negotiation status
5’b00100 - Port 4 Operating mode and Negotiation status
5’b00101 - Port 5 Operating mode and Negotiation status
5’b00110 - Port 6 Operating mode and Negotiation status
5’b00111 - Port 7 Operating mode and Negotiation status
5’b01000 - Port CPU Operating mode and Negotiation status
5’b01001 - Port MMAC Operating mode and Negotiation status
Zarlink Semiconductor Inc.
ZL50409
119
Data Sheet