zl50409 Zarlink Semiconductor, zl50409 Datasheet - Page 45

• Manufacturer Part Number: zl50409
• Description: Managed 9-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

dropped only if the system runs out of the specific buffer resource, per class buffer or per source port buffer. The
WRED thresholds of each queue can be programmed by the QOS control registers (refer to the register group 8).
See Programming QoS Registers application note, ZLAN-42, for more information.
7.4
Although traffic shaping is not a primary function of the ZL50409, the chip does implement a shaper for every queue
in the MMAC port. Our goal in shaping is to control the average rate of traffic exiting the ZL50409. If shaper is
enabled, strict priority will be applied to that queue. The priority between two shaped queue is the same as in strict
priority scheduling.
Traffic rate is set using a programmable whole number, no greater than 64. For example, if the setting is 32, then
the traffic rate transmit out of the shaped queue is 32/64 * 1000 Mbps = 500 Mbps. See Programming QoS Register
application note, ZLAN-42, for more information.
Also, when shaping is enabled, it is possible for a queue to explode in length if fed by a greedy source. The reason
is that a shaper is by definition not work-conserving; that is, it may hold back from sending a packet even if the line
is idle. Though we do have global resource management, we do nothing other than per port WRED to prevent this
situation locally. We assume the traffic is policed at a prior stage to the ZL50409 or WRED dropping is fine and shall
restrain this situation.
7.5
The ZL50409 provides a rate control function on its RMAC ports. The concept is much the same as shaping, except
that it applies to both ingress and egress directions and the control is per port rather than per queue. It provides a
way of reducing the total bandwidth of all frames received from or transmitted to a port, to a rate below wire speed.
As with shaping, the maximum burst size can also be configured.
Rate control may be a valuable feature on RMAC ports in access applications where the service provider would like
to limit the traffic received and transmitted by each port independently of each other, and independently of the
physical line rate. The service provider can then provide differential pricing, based on the negotiated bandwidth
requirements for each user. In such applications of the ZL50409, the MMAC port is viewed as an uplink port, where
rate control is not desired.
See Rate Control application note, ZLAN-33, for more information.
7.6
Because the number of FDB slots is a scarce resource, and because we want to ensure that one misbehaving
source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept
of buffer management into the ZL50409. Our buffer management scheme is designed to divide the total buffer
space into numerous reserved regions and one shared pool, as shown in Figure 11 on page 46.
As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames stores
frames prior to receiving a switch response. Such a temporary region is necessary, because when the frame first
enters the ZL50409, its destination port and class are as yet unknown, and so the decision to drop or not needs to
be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame
drop discipline after classifying.
Three priority sections, one for each pair of the first six priority classes, ensure a programmable number of FDB
slots per class. The lowest two classes do not receive any buffer reservation. Furthermore, a frame is stored in the
region of the FDB corresponding to its class. As we have indicated, the eight classes use only two transmission
scheduling queues for RMAC ports (four queues for the MMAC & CPU ports), but as far as buffer usage is
concerned, there are still eight distinguishable classes.
Another segment of the FDB reserves space for each of the 10 ports — 9 ports for Ethernet and one CPU port (port
number 8). Each port has it’s own programmable source port reservation. These 10 reserved regions make sure
that no well-behaved source port can be blocked by another misbehaving source port.
Shaper
Rate Control
Buffer Management
Zarlink Semiconductor Inc.
ZL50409
45
Data Sheet