zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 61
zl50405
Manufacturer Part Number
zl50405
Description
Managed5-port 10/100 M Ethernet Switch
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50405.pdf
(132 pages)
- Current page: 61 of 132
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MCCTH
RDRC0
RDRC1
RDRC2
SFCB
C1RS
C2RS
C3RS
AVPML
AVPMM
AVPMH
AVDM
TOSPML
TOSPMM
TOSPMH
TOSDML
USER_PROTOCOL_n
USER_PROTOCOL_
FORCE_DISCARD
WLPP10
WLPP32
WLPP54
WLPP76
WLPE
WLPFD
USER_PORTn_LOW
USER_PORTn_HIGH
USER_PORT1:0_
PRIORITY
Register
Multicast Congestion
Threshold
WRED Drop Rate Control 0
WRED Drop Rate Control 1
WRED Drop Rate Control 2
Share FCB Size
Class 1 Reserve Size
Class 2 Reserve Size
Class 3 Reserve Size
VLAN Priority Map Low
VLAN Priority Map Middle
VLAN Priority Map High
VLAN Discard Map
TOS Priority Map Low
TOS Priority Map Middle
TOS Priority Map High
TOS Discard Map
User Define Protocol n
User Define Protocol 0 To 7
Force Discard Enable
Well Known Logic Port 0
and 1 Priority
Well Known Logic Port 2
and 3 Priority
Well Known Logic Port 4
and 5 Priority
Well Known Logic Port 6
and 7 Priority
Well Known Logic Port 0 To
7 Enable
Well Known Logic Port 0 To
7 Force Discard Enable
User Define Logical Port n
Low
User Define Logical Port n
High
User Define Logic Port 0
and 1 Priority
Table 13 - Register Description (continued)
Description
Zarlink Semiconductor Inc.
ZL50405
61
CPU Addr
570+2n
571+2n
550+n
(Hex)
51A
51B
512
513
514
515
518
519
530
531
532
533
540
541
542
543
558
560
561
562
563
564
565
590
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0B3+n
09A+n
092+n
(Hex)
Addr
0BB
0AA
0AB
0AC
0AD
05C
05A
05B
05D
0A8
0A9
0A2
090
091
074
075
076
077
056
057
058
059
I²C
NA
NA
Default
003
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
Data Sheet
(n=0..7)
(n=0..7)
Notes
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