zl50405 Zarlink Semiconductor, zl50405 Datasheet - Page 83

no-image

zl50405

Manufacturer Part Number
zl50405
Description
Managed5-port 10/100 M Ethernet Switch
Manufacturer
Zarlink Semiconductor
Datasheet
Note: Strict priority applies between different selected queues (UQ3>UQ2>UQ1>UQ0>MQ3>MQ2>MQ1>MQ0).
12.3.4.11
CPU Address:h324
Accessed by CPU (RO)
CPU receive queue status
12.3.4.12
CPU Address:h325
Accessed by CPU (RW)
MAC01, MAC23, and MAC9 registers are used with the MAC0~5 registers to form the CPU MAC address on a per
port basis.
12.3.4.13
CPU Address:h326
Accessed by CPU (RW)
Bits [3:0]:
Bits [7:4]:
Bits [2:0]:
Bit [3]:
Bits [6:4]:
Bit [7]:
Bits [2:0]:
Bit [3]:
Bits [6:4]:
Bit [7]:
RQSS – Receive Queue Status
MAC01 – Increment MAC port 0,1 address
MAC23 – Increment MAC port 2,3 address
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Bits [42:40] of Port 2 CPU MAC address
Reserved
Bits [42:40] of Port 3 CPU MAC address
Reserved
Bits [42:40] of Port 0 CPU MAC address
Reserved
Bits [42:40] of Port 1 CPU MAC address
Reserved
Unicast Queue 3 to 0 not empty
0: Empty
1: Not Empty
Multicast Queue 3 to 0 not empty
Select Queue 2
Select Queue 3
Select Multicast Queue 0
Select Multicast Queue 1
Select Multicast Queue 2
Select Multicast Queue 3
Zarlink Semiconductor Inc.
ZL50405
83
Data Sheet

Related parts for zl50405