am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 152

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

Recommendation for Power and Ground
Decoupling
The mixed analog/digital circuitry in the PCnet-PCI
make it imperative to provide noise-free power and
ground connections to the device. Without clean power
and ground connections, a design may suffer from high
bit error rates or may not function at all. Hence, it is
highly recommended that the guidelines presented here
are followed to ensure a reliable design.
Decoupling/Bypass Capacitors: Adequate decoupling
of the power and ground pins and planes is required by
all PCnet-PCI designs. This includes both low-fre-
quency bulk capacitors and high frequency capacitors.
It is recommended that at least one low-frequency bulk
(e.g. 22 F) decoupling capacitor be used in the area of
The most critical pins in the layout of a PCnet-PCI
design are the 4 analog power and 2 analog ground
pins, AVDD[1–4] and AVSS[1–2], respectively. All of
these pins are located in one corner of the device, the
“analog corner.” Specific functions and layout require-
ments of the analog power and ground pins are given
below.
AVSS1 and AVDD3: These pins provide the power and
ground for the Twisted Pair and AUI drivers. In addition
AVSS1 serves as the ground for the logic interfaces in
the 20 MHz Crystal Oscillator. Hence, these pins can be
APPENDIX B
C
A
P
Via to the Power Plane
Via to the Ground Plane
Correct
VSS/VSSB
VDD/VDDB
PCnet
C
A
P
Am79C970
Correct
VDD/VDDB
VSS/VSSB
PCnet
the PCnet-PCI device. The bulk capacitor(s) should be
connected directly to the power and ground planes. In
addition, at least 8 high frequency decoupling capaci-
tors (e.g. 0.1 F multilayer ceramic capacitors) should
be used around the periphery of the PCnet-PCI device
to prevent power and ground bounce from affecting de-
vice operation. To reduce the inductance between the
power and ground pins and the capacitors, the pins
should be connected directly to the capacitors, rather
than through the planes to the capacitors. The sug-
gested connection scheme for the capacitors is shown
in the figure below. Note also that the traces connecting
these pins to the capacitors should be as wide as possi-
ble to reduce inductance (15 mils is desirable).
very noisy. A dedicated 0.1 F capacitor between these
pins is recommended.
AVSS2 and AVDD2: These pins are the most critical
pins on the PCnet-PCI device because they provide the
power and ground for the phase-lock loop (PLL) portion
of the chip. The voltage-controlled oscillator (VCO)
portion of the PLL is sensitive to noise in the 60 kHz –
200 kHz. range. To prevent noise in this frequency
range from disrupting the VCO, it is strongly recom-
mended that the low-pass filter shown below be imple-
mented on these pins.
C
A
P
Incorrect
VDD/VDDB
VSS/VSSB
PCnet
18220C-54
1-1019