am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 98

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

CSR32: Next Transmit Descriptor Address Lower
Bit
31–16 RES
15–0 NXDAL
CSR33: Next Transmit Descriptor Address Upper
Bit
31–16 RES
15–0 NXDAU
CSR34: Current Transmit Descriptor
Address Lower
Bit
31–16 RES
15–0 CXDAL
CSR35: Current Transmit Descriptor
Address Upper
Bit
31–16 RES
15–0 CXDAU
Name
Name
Name
Name
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
next TDRE address pointer.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
next TDRE address pointer.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
current TDRE address pointer.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
current TDRE address pointer.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
by
by
by
by
H_RESET,
H_RESET,
H_RESET,
H_RESET,
P R E L I M I N A R Y
Am79C970
CSR36: Next Next Receive Descriptor Address
Lower
Bit
31–16 RES
15–0 NNRDAL
CSR37: Next Next Receive Descriptor Address
Upper
Bit
31–16 RES
15–0 NNRDAU
CSR38: Next Next Transmit Descriptor Address
Lower
Bit
31–16 RES
15–0 NNXDAL
CSR39: Next Next Transmit Descriptor Address
Upper
Bit
31–16 RES
Name
Name
Name
Name
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
next next receive descriptor ad-
dress pointer.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
next next receive descriptor ad-
dress pointer.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
next next transmit descriptor ad-
dress pointer.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
S_RESET or STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
by
by
by
H_RESET,
H_RESET,
H_RESET,
AMD
1-965