am79c972b Advanced Micro Devices, am79c972b Datasheet - Page 110

• Manufacturer Part Number: am79c972b
• Description: Pcnet?-fast+ Enhanced 10/100 Mbps Pci Ethernet Controller With Onnow Support
• Manufacturer: Advanced Micro Devices

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TINTM
IDONM
RES
DXSUFLO
LAPPEN
or S_RESET and is not affected
by STOP.
Read/Write accessible always.
TINTM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
Read/Write accessible always.
IDONM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
When DXSUFLO (CSR3, bit 6) is
set to 0, the transmitter is turned
off when an UFLO error occurs
(CSR0, TXON = 0).
When DXSUFLO is set to 1, the
Am79C972 controller gracefully
recovers from an UFLO error. It
scans the transmit descriptor ring
until it finds the start of a new
frame and starts a new transmis-
sion.
Read/Write accessible always.
DXSUFLO
H_RESET or S_RESET and is
not affected by STOP.
Transmit
TINTM is set, the TINT bit will be
masked and unable to set the
INTR bit.
Initialization
IDONM is set, the IDON bit will be
masked and unable to set the
INTR bit.
Reserved location. Read and
written as zeros.
Disable Transmit Stop on Under-
flow error.
Look Ahead Packet Processing
Enable. When set to a 1, the
LAPPEN bit will
Am79C972 controller to generate
an interrupt following the descrip-
tor write operation to the first buff-
er of a receive frame. This
interrupt will be generated in ad-
dition to the interrupt that is gen-
erated following the descriptor
write operation to the last buffer
of a receive packet. The interrupt
Interrupt
is
Done
cleared
cause the
Mask.
Mask.
Am79C972
by
If
If
will be signaled through the RINT
bit of CSR0.
Setting LAPPEN to a 1 also en-
ables the Am79C972 controller to
read the STP bit of receive de-
scriptors. The Am79C972 con-
troller
information to determine where it
should begin writing a receive
packet’s data. Note that while in
this mode, the Am79C972 con-
troller can write intermediate
packet data to buffers whose de-
scriptors do not contain STP bits
set to 1. Following the write to the
last descriptor used by a packet,
the Am79C972 controller will
scan through the next descriptor
entries to locate the next STP bit
that is set to a 1. The Am79C972
controller will begin writing the
next packets data to the buffer
pointed to by that descriptor.
Note that because several de-
scriptors may be allocated by the
host for each packet, and not all
messages may need all of the de-
scriptors that are allocated be-
tween descriptors that contain
STP = 1, then some descriptors/
buffers may be skipped in the
ring. While performing the search
for the next STP bit that is set to
1, the Am79C972 controller will
advance through the receive de-
scriptor ring regardless of the
state of ownership bits. If any of
the entries that are examined
during
Am79C972 controller ownership
of the descriptor but also indicate
STP = 0, then the Am79C972
controller will reset the OWN bit
to 0 in these entries. If a scanned
entry indicates host ownership
with
Am79C972 controller will not al-
ter the entry, but will advance to
the next entry.
When the STP bit is found to be
true, but the descriptor that con-
tains this setting is not owned by
the Am79C972 controller, then
the Am79C972 controller will stop
advancing through the ring en-
STP = 0,
will
this
use
search
then
the
indicate
STP
the