am79c972b Advanced Micro Devices, am79c972b Datasheet - Page 97

• Manufacturer Part Number: am79c972b
• Description: Pcnet?-fast+ Enhanced 10/100 Mbps Pci Ethernet Controller With Onnow Support
• Manufacturer: Advanced Micro Devices

PC net- P CI II (A m 79C9 70A ) an d P Cnet - FAS T
(Am79C971) devices.
The PCI Device ID register is located at offset 02h in
the PCI Configuration Space. It is read only.
PCI Command Register
Offset 04h
The PCI Command register is a 16-bit register used to
control the gross functionality of the Am79C972 con-
troller. It controls the Am79C972 controller’s ability to
generate and respond to PCI bus cycles. To logically
disconnect the Am79C972 device from all PCI bus cy-
cles except configuration cycles, a value of 0 should be
written to this register.
The PCI Command register is located at offset 04h in
the PCI Configuration Space. It is read and written by
the host.
Bit
15-10
9
8
7
6
Name
RES
FBTBEN
SERREN
RES
PERREN
Description
Reserved locations. Read as ze-
ros; write operations have no ef-
fect.
Fast Back-to-Back Enable. Read
as zero; write operations have no
effect. The Am79C972 controller
will not generate Fast Back-to-
Back cycles.
SERR Enable. Controls the as-
sertion of the SERR pin. SERR is
disabled
cleared. SERR will be asserted
on detection of an address parity
error and if both SERREN and
PERREN (bit 6 of this register)
are set.
SERREN
H_RESET and is not effected by
S_RESET or by setting the STOP
bit.
Reserved location. Read as ze-
ros; write operations have no ef-
fect.
Parity Error Response Enable.
Enables the parity error response
functions. When PERREN is 0
and the Am79C972 controller de-
tects a parity error, it only sets the
Detected Parity Error bit in the
PCI Status register. When PER-
REN is 1, the Am79C972 control-
ler
detection of a data parity error. It
asserts
when
is
PERR
cleared
SERREN
on
Am79C972
the
by
is
5
4
3
2
1
VGASNOOP
MWIEN
SCYCEN
BMEN
MEMEN
also sets the DATAPERR bit (PCI
Status register, bit 8), when the
data parity error occurred during
a master cycle. PERREN also
enables reporting address parity
errors through the SERR pin and
the SERR bit in the PCI Status
register.
H_RESET and is not affected by
S_RESET or by setting the STOP
bit.
ro; write operations have no ef-
fect.
cle Enable. Read as zero; write
operations have no effect. The
Am79C972 controller only gener-
ates Memory Write cycles.
zero; write operations have no ef-
fect. The Am79C972 controller
ignores all Special Cycle opera-
tions.
BMEN enables the Am79C972
controller to become a bus mas-
ter on the PCI bus. The host must
set BMEN before setting the INIT
or STRT bit in CSR0 of the
Am79C972 controller.
and is not effected by S_RESET
or by setting the STOP bit.
The Am79C972 controller will ig-
nore all memory accesses when
MEMEN is cleared. The host
must set MEMEN before the first
memory access to the device.
host must program the PCI Mem-
ory Mapped I/O Base Address
register with a valid memory ad-
dress before setting MEMEN.
For accesses to the Expansion
ROM, the host must program the
PCI Expansion ROM Base Ad-
dress register at offset 30h with a
PERREN
VGA Palette Snoop. Read as ze-
Memory Write and Invalidate Cy-
Special Cycle Enable. Read as
Bus
BMEN is cleared by H_RESET
Memory Space Access Enable.
For memory mapped I/O, the
Master
is
Enable.
cleared
Setting
97
by