am79c901a Advanced Micro Devices, am79c901a Datasheet - Page 18

• Manufacturer Part Number: am79c901a
• Description: Homephy Single-chip 1/10 Mbps Home Networking Phy
• Manufacturer: Advanced Micro Devices

PIN DESCRIPTIONS
Configuration Pins
MII/GPSI
MII/GPSI
MII/GPSI selects between the MII and the GPSI inter-
face. This pin must be connected to either V
Changing the state of this pin is prohibited.
GM_MODE
GM_MODE
This input pin selects between the MDC/MDIO com-
mand and control interface and the SPI interface nor-
mally available in the GPSI mode. This pin must be
connected to either V
this pin is prohibited.
Note: GM_MODE = 1 overrides the value on the
MII/GPSI configuration pin.
PHY_AD
PHY Address
Sets bit 2 of the PHY Address field. The PHYs have de-
fault MII address of 0x00 (0000b) for the 1 Mbps
HomePNA PHY and 0x01 (0001b) for the 10BASE-T
PHY. If this bit is set, the address for the HomePNA
PHY is 0x02 (00010b) and 0x03 (00011b) for the
10BASE-T PHY.
ISOLATE
Isolate
In an environment that utilizes the MII or the SPI com-
mand and control interface (managed mode), this pin
must be held HIGH. In an environment that does not
use the MII or the SPI command and control interface
(external control mode), this pin enables the data inter-
face when set to a LOW, and forces the interface into a
high impedance state when held HIGH. This pin func-
tions in conjunction with the PHY_SEL pin and HPR0,
bit 10, and TBR0, bit 10.
PHY_SEL
PHY Select
In an environment that utilizes the MII or the SPI com-
mand and control interface (managed mode), this pin
must be held LOW. In an environment that does not use
18
GM_MODE
0
0
1
MII/GPSI
1
0
X
DD
or V
Interface
GPSI
GPSI
Data
MII
SS
. Changing the state of
Control Interface
Command and
MDC/MDIO
MDC/MDIO
P R E L I M I N A R Y
SPI
DD
or V
Input
Input
Input
Input
Input
Am79C901A
SS
.
the MII or the SPI command and control interface (ex-
ternal control mode), this pin selects which PHY data
and status signals will be driven onto the interface.
When set to a LOW, the HomePNA PHY data and sta-
tus signals will be driven onto the interface. When set
to a HIGH, the 10BASE-T PHY data and status signals
will be driven onto the interface. This pin functions in
conjunction with the ISOLATE pin.
Board Interface
LED_COL
LED_COL
This output is designed to directly drive an LED. COL
low indicates that a collision has been detected on
the currently active PHY. An internal pulse stretching
circuit will ensure that the minimum output pulse is
approximately 100 ms.
LED_ACTIVITY
LED_ACTIVITY
This output is designed to directly drive an LED.
ACTIVITY low indicates that there is receive or trans-
mit activity on the network of the currently active PHY.
An internal pulse stretching circuit will ensure that the
minimum output pulse is approximately 100 ms.
LED_LINK
LED_LINK
This output is designed to directly drive an LED. LINK
low indicates that a valid link has been detected on the
currently active PHY.
Managed Mode
External Control Mode
Bit 10
HPR0
1
0
1
0
1
1
1
LOW = 1 Mbps HomePNA PHY
HIGH = 10BASE-T PHY
Bit 10
TBR0
1
1
0
0
1
1
1
PHY_SEL
Don’t
Care
0
0
0
0
1
0
ISOLATE
1
1
1
1
0
0
1
HomePNA
10BASE-T
10BASE-T
HomePNA
Non Valid
Interface
Source
1 Mbps
1 Mbps
Hi Z
Hi Z
Output
Output
Output