am79c901a Advanced Micro Devices, am79c901a Datasheet - Page 26

• Manufacturer Part Number: am79c901a
• Description: Homephy Single-chip 1/10 Mbps Home Networking Phy
• Manufacturer: Advanced Micro Devices

Note: During the AID interval, TXCLK and RXCLK
stop for up to 140 s.
Serial Peripheral Interface (SPI-Slave)
Mode
When MII/GPSI is set to 0, the device is in “SPI” mode.
The device acts as an SPI slave peripheral in this mode
of operation. Commands are issued to the device by
asserting the CS signal (active low), shifting in an 4-bit
26
Idle (excluding
IPG time)
Preamble (first 64
bits of TX MAC
frame)
Data (throughout
the data phase)
IPG (96 bit times
following CRS
SCLK
SDO
Note: CLS may be asserted up to 120 s after RXCRS has been asserted. Once CLS has been asserted,
TXCLK and RXCLK run until 96 cycles after CLS and RXCRS are cleared. It can take a maximum of approxi-
mately 60 s for RXCRS to clear.
SDI
CS
Condition
RXCRS
RXCLK
RXDAT
TXDAT
TXCLK
TXEN
CLS
1
2
Table 2. GPSI Timing
CLK Period
3
583.3 ns
233.3 ns
233.3 ns
100 ns -
10 s
4
Op Codes
5
6
Figure 9. Operation of the SPI Interface
CLK Frequency
7
1.0 MHz avg.
Error Code
Figure 8. RXPKT - CLS Asserted
4.3 MHz
1.7 MHz
4.3 MHz
8
P R E L I M I N A R Y
9
Address
10
Am79C901A
11
12
opcode, followed by an 10-bit register address and
2 bits of end delimiter. If the operation is a write, the
data bits are written into the desired register. If the op-
eration is a read, then these data bits are ignored. The
SDO pin will shift out 16 data bits representing the con-
tents of the register referenced by the address field for
read operations. All commands must be initiated with a
high-to-low transition on the CS pin. Only one com-
mand can be sent in one CS cycle.
For assistance in debugging access to the SPI inter-
face, an error code is driven onto the SDO. If there is
less than 32 bits of SCLK during the time that CS is as-
serted, the error code field of SDO on the next com-
mand will indicate AAAA. When there is an incorrect
opcode in the command on SDI AAAA will be immedi-
ately driven out on SDO until CS deasserts. If there are
more than 32 clock cycles while CS is low, the first 32
are assumed to contain the data, and the additional
clock bits and associated data are ignored. In this case,
the SDO might generate AAAA under the additional
clock bits. See Figure 9.
13
14
15
16
17
Data Out
Data In
18
19
30
31
22304B-10
22304B-11
32