am79c901a Advanced Micro Devices, am79c901a Datasheet - Page 31

• Manufacturer Part Number: am79c901a
• Description: Homephy Single-chip 1/10 Mbps Home Networking Phy
• Manufacturer: Advanced Micro Devices

1 Mbps HomePNA PHY
The integrated HomePNA transceiver is a physical
layer device supporting HomePNA specification 1.0 for
home phoneline networking. It provides all of the PHY
layer functions required to support 1 Mbps data transfer
speeds over existing residential phone wiring.
All data bits are encoded into the relative time position
of a pulse with respect to the previous one. The wave-
form on the wire consists of a 7.5 MHz carrier sinusoid
enclosed within an exponential (bell shaped) enve-
lope. The waveform is produced by generating four
7.5 MHz square wave cycles and passing them
through an external bandpass filter.
The HomePNA PHY frame consists of a HomePNA
header that replaces the normal Ethernet 64-bit pream-
ble and delimiter. The frame header is prepended to a
standard Ethernet packet starting with the destination
address and ending with the CRC.
Only the PHY layer and its parameters are modified
from that of the standard Ethernet implementation. The
HomePNA PHY layer is designed to operate with a
standard Ethernet MAC layer controller implementing
all the CSMA/CD protocol features.
The frame begins with a characteristic SYNC interval
that delineates the beginning of a HomePNA frame fol-
lowed by an Access ID (AID) which encodes 8 bits of
AID and 4 bits of control word. The AID is used to de-
tect collisions and is dynamically assigned, while the
control word carries speed and power information.
The AID is followed by a silence interval, then 32 bits of
data reserved for PHY layer communication. These bits
are accessible via internal registers and are for future
use.
Data encoding consists of two symbol types: an AID
symbol and a data symbol. The AID symbol is always
transmitted at the same speed and encodes 2 bits that
determine the pulse position (one of four) relative to the
previous pulse. These bits are transmitted LSB first.
The access symbol interval is fixed.
P R E L I M I N A R Y
Am79C901A
The data symbol interval is variable. The arriving bit
stream is blocked into from 3-bit to 6-bit blocks accord-
ing to a proprietary (RLL25) algorithm. The bits in each
block are then used to encode a data symbol. Each
symbol consists of a Data Inter Symbol Blanking Inter-
val (DISBI) and then a pulse at one of 25 possible po-
sitions. The bits in the data block determine the pulse
position. Immediately after the pulse a new symbol in-
terval begins. During the DISBI the receiver ignores all
incoming pulses to allow network reflections to die out.
Any station may be programmed to assume the role of
a PHY master and remotely command, via the control
word, the rest of the units on the network to change
their transmit speed or power level.
Many of the framing parameters are programmable in
the HomePNA PHY and will allow modifications to
transmission speed center frequency as well as noise
and reflection rejection algorithms.
Two default speeds are provided, low at 0.7 Mbps and
high at 1 Mbps.
HomePNA PHY Medium Interface
Framing
The HomePNA frame on the phone wire network con-
sists of a header generated in the PHY prepended to
an IEEE 802.3 Ethernet data packet received from the
MAC layer. See Figure 16.
When transmitting on the phone wire pair, the
HomePNA PHY first receives an Ethernet MAC frame
from the MAC. The 8 octets of preamble and delimiter
are stripped off and replaced with the HomePNA PHY
header described below, then transmitted on the
home network with the LSB of each symbol being
transmitted first.
During a receive operation, the reverse process is exe-
cuted. When a HomePNA PHY frame is received by
the PHY, the header is stripped off and replaced with
the 4 octets of preamble and delimiter of the IEEE
802.3 Ethernet MAC frame specification and then
passed on to the MAC layer.
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