s71gs256nc0bawak0 Meet Spansion Inc., s71gs256nc0bawak0 Datasheet - Page 109

• Manufacturer Part Number: s71gs256nc0bawak0
• Description: Stacked Multi-chip Product Mcp 256/128 Megabit 16/8m X 16-bit Cmos 3.0 Volt Vcc And 1.8 V Vio Mirrorbit Tm Uniform Sector Page-mode Flash Memory With 64/32 Megabit 4/2m X 16-bit 1.8v Psram
• Manufacturer: Meet Spansion Inc.

A d v a n c e
I n f o r m a t i o n
CE#
OE#
WE#
ADDRESS
Address Valid
Data Valid
DATA
LB#/UB#
t WC = WRITE Cycle Time
Don't Care
Figure 24. WRITE Operation (ADV# LOW)
Page Mode READ Operation
Page mode is a performance-enhancing extension to the legacy asynchronous
READ operation. In page mode-capable products, an initial asynchronous read
access is performed, then adjacent addresses can be read quickly by simply
changing the low-order address. Addresses A[3: 0] are used to determine the
members of the 16-address CellularRAM page. Addresses A[4] and higher must
remain fixed during the entire page mode access.
Figure 25
shows the timing for
a page mode access. Page mode takes advantage of the fact that adjacent ad-
dresses can be read in a shorter period of time than random addresses. WRITE
operations do not include comparable page mode functionality.
During asynchronous page mode operation, the CLK input must be held LOW .
CE# must be driven HIGH upon completion of a page mode access. WAIT will be
driven while the device is enabled and its state should be ignored. Page mode is
enabled by setting RCR[ 7] to HIGH. WRITE operations do not include comparable
page mode functionality. ADV must be driven LOW during all page mode read
accesses.
CellularRAM Type 2
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October 4, 2004 cellRAM_00_A0