s71gs256nc0bawak0 Meet Spansion Inc., s71gs256nc0bawak0 Datasheet - Page 174

• Manufacturer Part Number: s71gs256nc0bawak0
• Description: Stacked Multi-chip Product Mcp 256/128 Megabit 16/8m X 16-bit Cmos 3.0 Volt Vcc And 1.8 V Vio Mirrorbit Tm Uniform Sector Page-mode Flash Memory With 64/32 Megabit 4/2m X 16-bit 1.8v Psram
• Manufacturer: Meet Spansion Inc.

Note: Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing di-
agrams for detailed information.
174
DQ[15:0]
A[ 21:0]
Symbol
A[21:0]
V
WE#
WE#
OE#
UB#
OE#
UB#
ZZ#
CE#
LB#
ZZ#
CE#
V
V
LB#
CC
CC
SS
Q
ation altogether and is used when no vital information is stored in the device.
These three refresh mechanisms are accessed through the CR.
Control
Logic
Output
Supply
Supply
Supply
Input/
Input
Input
Input
Input
Input
Input
Input
Type
Address Inputs: Inputs for the address accessed during READ or WRITE operations. The
address lines are also used to define the value to be loaded into the configuration register.
Sleep Enable: When ZZ# is LOW , the configuration register can be loaded or the device can
enter one of two low-power modes (DPD or PAR).
Chip Enable: Activates the device when LOW . When CE# is HIGH, the device is disabled and
goes into standby power mode.
Output Enable: Enables the output buffers when LOW . When OE# is HIGH, the output
buffers are disabled.
Write Enable: Enables WRITE operations when LOW .
Lower Byte Enable. DQ[7:0]
Upper Byte Enable. DQ[ 15: 8]
Data Inputs/ Outputs.
Device Power Supply: (1.7 V–1.95 V) Power supply for device core operation.
V
I/O Power Supply: (1.8 V) Power supply for input/output buffers.
SS
must be connected to ground.
Address Decode
Configuration
Register (CR)
Figure 64. Functional Block Diagram
Logic
Table 65. Pin Descriptions
A d v a n c e
CellularRAM-2A
4,096K x 16
Memory
DRAM
Array
I n f o r m a t i o n
Description
Output
Buffers
Input/
MUX
and
cellRAM_02_A0 December 15, 2004
DQ[7:0]
DQ[15:8]