s71gs256nc0bawak0 Meet Spansion Inc., s71gs256nc0bawak0 Datasheet - Page 176

• Manufacturer Part Number: s71gs256nc0bawak0
• Description: Stacked Multi-chip Product Mcp 256/128 Megabit 16/8m X 16-bit Cmos 3.0 Volt Vcc And 1.8 V Vio Mirrorbit Tm Uniform Sector Page-mode Flash Memory With 64/32 Megabit 4/2m X 16-bit 1.8v Psram
• Manufacturer: Meet Spansion Inc.

Functional Description
Bus Operating Modes
176
Power-Up Initialization
Asynchronous Mode
The 64Mb async/page CellularRAM device is a high-density alternative to SRAM
and Pseudo SRAM products, popular in low-power, portable applications. The de-
vice contains 67,108,864 bits organized as 4,194,304 addresses by 16 bits. It
includes the industry-standard, asynchronous memory interface found on other
low-power SRAM or Pseudo SRAM offerings. Page mode accesses are also in-
cluded as a bandwidth-enhancing extension to the asynchronous read protocol.
CellularRAM products include an on-chip voltage sensor that is used to launch the
power-up initialization process. Initialization will load the CR with its default set-
tings. V
stable level above 1.70 V , the device requires 150 µs to complete its self initial-
ization process (see Figure 2). During the initialization period, CE# should remain
HIGH. When initialization is complete, the device is ready for normal operation.
At power-up, the CR is set to 0070h.
CellularRAM products incorporate the industry-standard, asynchronous interface
found on other low-power SRAM or Pseudo SRAM offerings. This bus interface
supports asynchronous READ and WRITE operations as well as the bandwidth-
enhancing page mode READ operation. The specific interface that is supported is
defined by the value loaded into the CR.
CellularRAM products power up in the asynchronous operating mode. This mode
uses the industry standard SRAM control interface (CE# , OE# , WE# , LB# / UB# ) .
READ operations
LOW while keeping WE# HIGH. Valid data will be driven out of the I/ Os after the
specified access time has elapsed. WRITE operations
CE#, WE#, and LB#/ UB# are driven LOW. During WRITE operations, the level
of OE# is a “Don't Care”; WE# will override OE#. The data to be written will be
latched on the rising edge of CE# , WE# , or LB#/UB# (whichever occurs first).
V CC Q
V CC
CC
and V
V CC = 1.7 V
CCQ
(Figure
Figure 65. Power-Up Initialization Timing
must be applied simultaneously, and when they reach a
66) are initiated by bringing CE# , OE#, and LB# / UB#
A d v a n c e
Device Initialization
t PU > 150 µs
CellularRAM-2A
I n f o r m a t i o n
Device ready for
normal operation
(Figure
67) occur when
cellRAM_02_A0 December 15, 2004