mh1020 Music Semiconductors, Inc., mh1020 Datasheet - Page 14

• Manufacturer Part Number: mh1020
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

The Memory Array
Memory Organization
The Memory array is organized into 64-bit words with
each word having an additional two validity bits. By
default, all words are configured to be 64 CAM cells.
However, bits 8–6 of the Control register can divide each
word into a CAM field and a RAM field. The RAM field
can be assigned to the least-significant or most-significant
portion of each entry.
The CAM/RAM partitioning is allowed on 16-bit
boundaries, permitting selection of the configuration
shown in Control Register Bits on page 24, bits 8–6 (e.g.,
“001” sets the 48 MSBs to CAM and the 16 LSBs to
RAM). Memory Array bits designated as RAM can be
used to store and retrieve data associated with the CAM
content at the same memory location.
DQ15–0
DQ15-0
/CM
/ EC
/W
/ E
/CM
/ EC
/W
/ E
Figure 6: Read Cycle
Figure 7: Write Cycle
data
14
Memory Access
There are two general ways to get data into and out of the
Memory array: directly or by moving the data by means of
the Comparand or Mask registers.
The first way, through direct reads or writes, is set up by
issuing a Set Persistent Destination (SPD) or Set Persistent
Source (SPS) command. The addresses for the direct
access can be supplied directly; supplied from the Address
register, supplied from the Next Free Address register, or
supplied
Additionally, all the direct writes can be masked by either
Mask register.
The second way is to move data by means of the
Comparand or Mask registers. This is accomplished by
issuing Data Move commands (MOV). Moves using the
Comparand register can also be masked by either of the
Mask registers.
Data
as
the
Highest-Priority
Match
address.
Rev. 1