mh1020 Music Semiconductors, Inc., mh1020 Datasheet - Page 15

• Manufacturer Part Number: mh1020
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

I/O Cycles
The MH supports four basic I/O cycles: Data Read, Data
Write, Command Read, and Command Write. The states
of the /W and /CM control inputs determine the type of
cycle. These signals are registered at the beginning of a
cycle by the falling edge of /E. Table 1 on page 3 shows
how the /W and /CM signals select the cycle type.
During Read cycles, the DQ15–0 outputs are enabled after
/E goes LOW. During Write cycles, the data or command
to be written is captured from DQ15–0 at the beginning of
the cycle by the falling edge of /E. Figure 9 on page 16 and
Figure 6 on page 14, show Read and Write cycles
respectively. Figure 7 on page 14, shows typical
cycle-to-cycle timing with the Match flag valid at the end
of the Comparand Write. Data writes and reads to the
comparand, Mask registers, or memory occur in one to
four 16-bit cycles, depending on the settings in the
Segment Control register. The Compare operation
automatically occurs during Data writes to the Comparand
or Mask registers when the destination segment counter
reaches the end count set in the Segment Control register.
If there was a match, the second cycle reads status or
associated data, depending on the state of /CM. For
cascaded devices, /EC needs to be LOW at the start of the
cycle prior to any cycle that requires a locked daisy chain,
such as a Status register or associated data read after a
match. If there is no match in Standard mode, the output
buffers stay High-Z, and the daisy chain must be unlocked
by taking /EC HIGH during a NOP or other
non-functioning cycle, as indicated in Table 4 on page 11.
Figure 8 on page 15 shows how the internal /EC timing
holds the daisy chain locking effect over into the next
cycle. In Enhanced mode, this NOP is not needed before
data or command writes following a non-matching
compare, as indicated by Table 4 on page 11. A
single-chip system does not require daisy-chained match
Rev. 1
/MA, /MM
DQ15–0
/CM
/MF
/EC
/W
/E
DATA
Figure 8: Cycle-to-Cycle Timing Example
COMPARAND WRITE
CYCLE
15
STATUS READ
flag operation, hence /EC could be tied HIGH and the
/MA pin or flag in the Status register used instead of /MF,
allowing access to the device regardless of the match
condition.
The minimum timings for the /E control signal are given
in Table 9 on page 28. Note that at minimum timings the
/E signal is non-symmetrical and that different cycle types
have different timing requirements, as given in Table 6 on
page 23.
DATA
CYCLE
/MA AND /MM FLAGS UPDATED
MATCH FLAG VALID
ASSOCIATED DATA
READ CYCLE
DATA