mh1020 Music Semiconductors, Inc., mh1020 Datasheet - Page 21

• Manufacturer Part Number: mh1020
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

INSTRUCTION SET SUMMARY
Mnemonic Format: INS dst, src[msk], val
INS: Instruction mnemonic
dst: Destination of the data
src: Source of the data
msk: Mask register used
val: Validity condition set at the location written
Instruction: Select Persistent Source
Instruction: Select Persistent Destination
Rev. 1
Operation
Comparand Register
Mask Register 1
Mask Register 2
Memory Array at Addr. Reg.
Memory Array at Address
Mem. at Highest-Priority Match
Operation
Comparand Register
Mask Register 1
Mask Register 2
Mem. at Addr. Reg. set Valid
Mem. at Addr. Reg. set Empty
Mem. at Addr. Reg. set Skip
Mem. at Addr.Reg. set Random
Memory at Address set Valid
Memory at Address set Empty
Memory at Address set Skip
Memory at Address set Random
Mem. at Highest-Prio. Match, Valid SPD M@HM,V
Mem. at Highest-Prio. Match, Emp. SPD M@HM,E
Masked by MR1
Masked by MR2
Masked by MR1
Masked by MR2
Masked by MR1
Masked by MR2
Masked by MR1
Masked by MR2
Masked by MR1
Masked by MR2
Masked by MR1
Masked by MR2
Masked by MR1
Masked by MR2
Masked by MR1
Masked by MR2
Masked by MR1
Masked by MR2
Masked by MR1
Masked by MR2
Masked by MR1
Masked by MR2
Mnemonic
SPS CR
SPS MR1
SPS MR2
SPS M@[AR]
SPS M@aaaH
SPS M@HM
Mnemonic
SPD CR
SPD CR[MR1]
SPD CR[MR2]
SPD MR
SPD MR2
SPD M@[AR],V
SPD M@[AR][MR1],V
SPD M@[AR][MR2],V
SPD M@[AR],E
SPD M@[AR][MR1],E
SPD M@[AR][MR2],E
SPD M@[AR],S
SPD M@[AR][MR1],S
SPD M@[AR][MR2],S
SPD M@[AR],R
SPD M@[AR][MR1],R
SPD M@[AR][MR2],R
SPD M@aaaH,V
SPD M@aaaH[MR1],V
SPD M@aaaH[MR2],V
SPD M@aaaH,E
SPD M@aaaH[MR1],E
SPD M@aaaH[MR2],E
SPD M@aaaH,S
SPD M@aaaH[MR1],S
SPD M@aaaH[MR2],S
SPD M@aaaH,R
SPD M@aaaH[MR1],R
SPD M@aaaH[MR2],R
SPD M@HM[MR1],V
SPD M@HM[MR2],V
SPD M@HM[MR1],E
SPD M@HM[MR2],E
Op-Code
Op-Code
012CH
016CH
01ACH
012DH
016DH
01ADH
0000H
0001H
0002H
0004H
0804H
0005H
0100H
0140H
0180H
0108H
0110H
0124H
0164H
01A4H
0125H
0165H
01A5H
0126H
0166H
01A6H
0127H
0167H
01A7H
0924H
0964H
09A4H
0925H
0965H
09A5H
0926H
0966H
09A6H
0927H
0967H
09A7H
21
Instruction: Select Persistent Destination
Instruction: Temporary Command Override
Instruction: Data Move
Operation
Mem. at Highest-Prio. Match, Skip SPD M@HM,S
Mem. at High.-Prio. Match, Random
Mem. at Next Free Addr., Valid
Mem. at Next Free Addr., Empty
Mem. at Next Free Addr., Skip
Mem. at Next Free Addr., Random SPD M@NF,R
Operation
Control Register
Page Address Register
Segment Control Register
Read Next Free Address
Address Register
Device Select Register
Read Persistent Source
Read Persistent Destination
Operation
Comparand Register from:
Mask Register 1 from:
Masked by MR1
Masked by MR2
Masked by MR1
Masked by MR2
Masked by MR1
Masked by MR2
MaskedbyMR1
MaskedbyMR2
Masked by MR1
Masked by MR2
Masked by MR1
Masked by MR2
No Operation
Mask Register 1
Mask Register 2
Memory at Address Reg.
Memory at Address
Mem. at Highest-Prio. Match
Comparand Register
No Operation
Mask Register 2
Memory at Address Reg.
Memory at Address
Mem. at Highest-Prio. Match
Masked by MR1
Masked by MR2
Masked by MR1
Masked by MR2
MaskedbyMR1
MaskedbyMR2
Mnemonic
SPD M@HM[MR1],S
SPD M@HM[MR2],S
SPD M@HM,R
SPD M@HM[MR1],R
SPD M@HM[MR2],R
SPD M@NF,V
SPD M@NF[MR1],V
SPD M@NF[MR2],V
SPD M@NF,E
SPD M@NF[MR1],E
SPD M@NF[MR2],E
SPD M@NF,S
SPD M@NF[MR1],S
SPD M@NF[MR2],S
SPD M@NF[MR1],R
SPD M@NF[MR2],R
Mnemonic
TCO CT
TCO PA
TCO SC
TCO NF
TCO AR
TCO DS
TCO PS
TCO PD
Mnemonic
NOP
MOV CR,MR1
MOV CR,MR2
MOV CR,[AR]
MOV CR,[AR][MR1]
MOV CR,[AR][MR2]
MOV CR,aaaH
MOV CR,aaaH[MR1]
MOV CR,aaaH[MR2]
MOV CR,HM
MOV CR,HM[MR1]
MOV CR,HM[MR2]
MOV MR1,CR
NOP
MOV MR1,MR2
MOV MR1,[AR]
MOV MR1,aaaH
MOV MR1,HM
Op-Code
Op-Code
Op-Code
(contin-
01AEH
0B0CH
012EH
016EH
012FH
016FH
01AFH
01B4H
01B5H
01B6H
01B7H
0B04H
0B44H
0B84H
030AH
030CH
030DH
0134H
0174H
0135H
0175H
0136H
0176H
0137H
0177H
0200H
0208H
0210H
0218H
0220H
0228H
0230H
0238H
0300H
0301H
0302H
0304H
0344H
0384H
0305H
0345H
0385H
0308H
0309H