tfra84j13 ETC-unknow, tfra84j13 Datasheet - Page 13

• Manufacturer Part Number: tfra84j13
• Description: Ultraframer Ds3/e3/ds2/e2/ds1/e1/ds0
• Manufacturer: ETC-unknow

TFRA84J13 Ultraframer
DS3/E3/DS2/E2/DS1/E1/DS0
5.6.4 Signaling Processor
The signaling processor supports the following modes:
Signaling features supported per channel are as follows:
Voice and data channels are programmable in the DS1
robbed-bit signaling modes. The entire payload can be
forced into a data-only (no signaling channels) mode i.e.,
transparent mode, achieved by programming one control
bit.
Signaling access occurs through the on-chip signaling reg-
isters or the system interface. Data and its associated sig-
naling information can be accessed through the system in
either DS1 or CEPT-E1 modes.
5.6.5 Facility Data Link (FDL) Processor
The receive facility data link processor monitors the bit-ori-
ented ESF data-link messages defined in ANSI T1.403.
The transmit facility data link unit overrides the FDL-FIFO
for the transmission of the bit-oriented ESF data-link mes-
sages defined in ANSI T1.403-1995.
13
13
Superframe (D4, SLC-96): 2-state, 4-state, and 16-state
VT 1.5 SPE: 2-state, 4-state, and 16-state
Extended superframe: 2-state, 4-state, and 16-state
CEPT: common channel signaling (CCS) (TS-16)
Transparent (pass through) signaling
J-ESF handling groups
Signaling debounce
Signaling freeze
Signaling interrupt upon change of state
Associated signaling mode (ASM)
Signaling inhibit
Signaling stomp
The FDL processor extracts and stores data link bits from
three different frame types as follows:
The respective bits are always extracted from frame-
aligned frames and are stored in a stack. The processor
controls notification of stack updates through the interrupt
(maskable) registers.
The transmit FDL functional block performs the transmis-
sion of D-bits into SLC-96 superframes, Sa-bits in CEPT
frames, and D-bits in DDS frames.
5.6.6 HDLC Unit
The HDLC processor formats the HDLC packets for inser-
tion into the programmable channels. A channel can be any
number of bits (1 to 8) from a time slot.
The maximum number of channels is 64. The maximum
channel bit rate is 64 kbits/s. The minimum channel bit rate
is 4 kbits/s. Each channel is allocated 128 bytes of storage.
HDLC processing of data on the facility data link (PRMs,
Sa-bits, or otherwise) is implemented by assigning the FDL
bit position to a logical HDLC channel.
D-bits and delineator bits from the SLC-96 multi-super-
frame.
Data link bits from DDS frames (bit 6 of time slot 24).
Two multiframes of Sa[4:8] bits from time slot 0 in CEPT
basic and CRC-4 multiframes.
In SLC-96 frames, the D and delineator bits are always
sourced from this functional block when the block is
enabled for insertion.
In DDS frames, the data link bits are always sourced
from this functional block when this block is enabled for
insertion. This functional block also provides the capabil-
ity to transmit BOMs (bit-oriented messages) in the data
link channel of ESF links.
In CEPT frames, the Sa bits are sourced from either the
Sa stack within this functional block or from the system
interface. The data link functional block only responds
with valid data when selected by the Sa source control
bits.
Product Description, Revision 4
Agere Systems Inc.
April 29, 2005