tfra84j13 ETC-unknow, tfra84j13 Datasheet - Page 8

• Manufacturer Part Number: tfra84j13
• Description: Ultraframer Ds3/e3/ds2/e2/ds1/e1/ds0
• Manufacturer: ETC-unknow

TFRA84J13 Ultraframer
DS3/E3/DS2/E2/DS1/E1/DS0
4.2 DS3/E3 to/from DS0/E0 Application
Figure 9-2 shows 2016 DS0/1536 E0s input via CHI or PSB. The DS0s/E0s are DS1/E1 framed, multiplexed to three DS3/
E3s, and then framed and output to DS3/E3 LIUs. The following points describe this scenario:
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2016 DS0/1536 E0s are input from a switch, DS1/E1 framed, then MUXed to x3 DS3/E3. These are then framed and out-
put to three DS3/E3 LIUs.
Similarly, three DS3/E3s are input from the LIUs, deMUXed to the DS1/E1 level, and output as 2016 DS0/1536 E0s.
The DS3s/E3s will be received/transmitted by the device via the DS3DATAIN/OUT pins.
The DS0s/E0s will be received/transmitted by the device via the CHIRX/TXDATA pins.
The system interface can be the CHI (concentrated highway interface) or PSB (parallel system bus):
— CHI can be programmed to operate at 8.192 MHz or 16.384 MHz clock and data rates.
— The PSB interface consists of a 16-bit wide parallel bus operating at 19.44 Mbits/s.
All three instances of the 28/21 channel M13/E13 MUXs are configured identically for M13/E13 mode.
All three instances of the 28/21 channel framers are configured identically for switching mode of operation.
DS3 to/from E1 to/from E0 application is also possible (x3 DS3 to/from 2016 E0s).
REF CLK
DS3/E3 LIU
Figure 4-2. x3 DS3s/E3s to/from 2016 DS0s/1536 E0s Configuration
TSWC01622
CLK GEN
x3 DS3/E3
ULTRAFRAMER
SYSTEM INTERFACE
(CHI OR PSB)
Product Description, Revision 4
SWITCH
DS0/E0
Agere Systems Inc..
April 29, 2005