tfra84j13 ETC-unknow, tfra84j13 Datasheet - Page 5

• Manufacturer Part Number: tfra84j13
• Description: Ultraframer Ds3/e3/ds2/e2/ds1/e1/ds0
• Manufacturer: ETC-unknow

TFRA84J13 Ultraframer
DS3/E3/DS2/E2/DS1/E1/DS0
2.5 DS1/E1 Digital Jitter Attenuation (DJA)
5 5
One to any number of loopbacks are supported for up to
84/63 channels in DS1/E1 channels from the M13/E13
and framer functional blocks. One-to-one loopback is
supported in all DS1/E1 channels. One-to-one loopback
is supported for DS3/E3 channels from the M13/E13
functional blocks.
Loopbacks can be configured to sectionalize a circuit for
identifying faults or misconfiguration during out of service
maintenance.
Fast alarm channels are supported for E13 and M13 to
framer interconnects for alarm indication signal (AIS or
blue alarm). This feature reduces the propagation delay
of the alarms by eliminating multiple integration of alarm
conditions.
Supports framer-only, transport (framer LIU, M13, and
E13), and switching (CHI and PSB) modes of operation.
The PLL bandwidth, damping factor, and sampling rates
are programmable.
Configurable to meet jitter and MTIE requirements.
Supports one DJA per each DS1/E1. (Note that the DJA
may not be cascaded.) There are 28/21 DJA channels
per block.
(3x28/21)
2.6 Microprocessor Unit (MPU) (x1)
2.7 JTAG
21-bit address/16-bit data bus microprocessor interface
(little-endian).
Synchronous (16 MHz to 66 MHz)/asynchronous micro-
processor interface modes.
Microprocessor data bus parity monitoring.
Summary of two level priority interrupts from the E13
block (maskable).
Global configuration of network performance monitoring
counters operation.
Global software resets.
Global enabling and powerdown of major functional
blocks.
Registers provisionable for clear on read/clear on write.
Compatible with most industry-standard processors.
IEEE
®
1149.1 JTAG boundary scan.
Product Description, Revision 4
Agere Systems Inc.
April 29, 2005