hi-8282 Holt Integrated Circuits, Inc., hi-8282 Datasheet
hi-8282
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hi-8282 Summary of contents
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... March 2007 GENERAL DESCRIPTION The HI-8282 is a silicon gate CMOS device for interfacing the ARINC 429 serial data bus to a 16-bit parallel data bus. Two receivers and an independent transmitter are provided. The receiver input circuitry and logic are designed to meet the ARINC 429 specifications for loading, level detection, timing, and protocol ...
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... INPUT CWSTR INPUT CLK INPUT TX CLK OUTPUT MR INPUT HI-8282 DESCRIPTION +5V ±5% ARINC receiver 1 positive input ARINC receiver 1 negative input ARINC receiver 2 positive input ARINC receiver 2 negative input Receiver 1 data ready flag Receiver 2 data ready flag Receiver data byte selection (0 = BYTE BYTE 2) ...
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... FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER The HI-8282 contains 10 data flip flops whose D inputs are con- nected to the data bus and clocks connected to flip flop provides options to the user as follows: DATA BUS FUNCTION CONTROL PIN If enabled, an internal connection BDO5 SELF TEST 0 = ENABLE ...
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... PULSE FALL TIME 1.5 ± 0.5 µsec PULSE WIDTH 5 µsec ± 5% The HI-8282 accepts signals within these tolerances and rejects signals outside these tolerances. Receiver logic achieves this as described below accurate 1MHz clock source is required to validate re- ceive signal timing. Less than 0.1% error is recommended. ...
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... X 31 FIFO DATA BUS FIGURE 3. TRANSMITTER BLOCK DIAGRAM HI-8282 TRANSMITTER PARITY The parity generator counts the ONES in the 31-bit word. If the BD12 control word bit is set low, the 32nd bit transmitted will make parity odd. If the control bit is high, the parity is even. ...
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... FUNCTIONAL DESCRIPTION (cont.) REPEATER OPERATION Repeater mode of operation allows a data word received by the HI-8282 to be placed directly into the Transmit FIFO for transmission. After a 32-bit word has been shifted into the receiver shift register, the D/R flag goes low. A logic "0" is placed ...
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... ENDAT 429DO or 429DO BIT 32 429DI D D/R D/REN EN t SELEN SEL DON'T CARE t ENPL PL1 PL2 TX/R ENTX 429DO HI-8282 TRANSMITTER OPERATION BYTE 1 VALID t DWSET t DWHLD PL12 TRANSMITTING DATA ARINC BIT DATA DATA BIT 1 BIT 2 REPEATER OPERATION TIMING t END ENEN ...
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... Logic "0" Output Voltage Output Current: (Bi-directional Pins) Output Current: (All Other Outputs) Output Capacitance: SUPPLY INPUT Standby Supply Current: Operating Supply Current: HI-8282 -0.3V to +7V Power Dissipation -29V to +29V Operating Temperature Range: (Industrial) -0.3V to Vcc +0.3V Storage Temperature Range: 10mA CONDITIONS SYMBOL ...
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... Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): High Speed Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): Low Speed Delay - 32nd ARINC Bit to TX/R HIGH Spacing - TX/R HIGH to ENTX L0W REPEATER OPERATION TIMING Delay - TX/R LOW to ENTX HIGH Master Reset Pulse Width ARINC Data Rate and Bit Timing HI-8282 + SYMBOL Pulse Width - CWSTR t CWSTR CWSTR ...
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... ADDITIONAL HI-8282 PIN CONFIGURATIONS (See page 1 for the 40-pin Ceramic Side-Brazed DIP Package ) 44-PIN PLASTIC PLCC HI-8282J-44 HI-8282JT-44 44-PIN CERAMIC LCC HI-8282 44-PIN J-LEAD CERQUAD HI-8282S HI-8282ST HI-8282SM-01 HOLT INTEGRATED CIRCUITS 10 HI-8282U HI-8282UT ...
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... NOT RECOMMENDED FOR NEW DESIGNS. The newer HI-8282APJI and HI-8282APJT replace the HI-8282J-44 and HI-8282JT-44 respectively. The HI-8282A parts are rated as Moisture Sensitive Level 1 (MSL 1) and do not require any special handling. The older HI- 8282J-44 and HI-8282JT-44 are rated as MSL 3 and require dry-packaging and /or bake-out in accordance with IPC/JEDEC J-STD-020A. HI-8282 ...
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... J-LEAD CERQUAD .650 ±.010 (16.510 ±.254) SQ. .039 ±.005 (.990 ±.127) .019 ±.002 (.483 ± .051) HI-8282 PACKAGE DIMENSIONS 2.020 max (51.308) .595 ±.010 (15.113 ±.254) .050 typ (1.270) .085 ±.009 (2.159 ± ...
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... SQ. BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-8282 PACKAGE DIMENSIONS PIN NO. 1 IDENT .045 x 45° .653 ±.004 (16.586 ±.102) SQ. See Detail A .610 ±.020 (15.494± ...