hi-8282 Holt Integrated Circuits, Inc., hi-8282 Datasheet - Page 4

• Manufacturer Part Number: hi-8282
• Description: Serial Transmitter And Dual Receiver
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION (cont.)
BIT TIMING
The ARINC 429 specification defines the following timing toler-
ances for received data:
The HI-8282 accepts signals within these tolerances and rejects
signals outside these tolerances. Receiver logic achieves this as
described below:
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
1. An accurate 1MHz clock source is required to validate re-
ceive signal timing. Less than 0.1% error is recommended.
2. The receiver uses three separate 10-bit sampling shift
registers for Ones detection, Zeros detection and Null detec-
tion. When the input signal is within the differential voltage
range for any shift register’s state (One Zero or Null) sam-
pling clocks a high bit into that register. When the receive sig-
nal is outside the differential voltage range defined for any
shift register, a low bit is clocked. Only one shift register can
clock a high bit for any given sample. All three registers
clock low bits if the differential input voltage is between de-
fined state voltage bands. Valid data bits require at least
three consecutive One or Zero samples (three high bits) in
the upper half of the Ones or Zeros sampling shift register,
and at least three consecutive Null samples (three high bits)
in the lower half of the Null sampling shift register within the
data bit interval. A word gap Null requires at least three con-
secutive Null samples (three high bits) in the upper half of
the Null sampling shift register and at least three consecu-
tive Null samples (three high bits) in the lower half of the
Null sampling shift register. This guarantees the minimum
pulse width.
DECODER
CONTROL
BITS
SEL
D/R
EN
ZEROS
ONES
NULL
/
100K BPS ± 1%
HIGH SPEED
1.5 ± 0.5 µsec
1.5 ± 0.5 µsec
5 µsec ± 5%
CONTROL
CONTROL
ENABLE
LATCH
MUX
EOS
BITS 9 & 10
SHIFT REGISTER
SHIFT REGISTER
SHIFT REGISTER
34.5 to 41.7 µsec
FIGURE 2.
12K -14.5K BPS
LOW SPEED
10 ± 5 µsec
10 ± 5 µsec
32 BIT SHIFT REGISTER
HOLT INTEGRATED CIRCUITS
32 TO 16 DRIVER
32 BIT LATCH
TO PINS
RECEIVER BLOCK DIAGRAM
HI-8282
4
WORD GAP
BIT CLOCK
RECEIVER PARITY
The receiver parity circuit counts Ones received, including the
parity bit. If the result is odd, a "0" appears in the 32nd bit.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). If the receiver decoder is enabled and the
9th and 10th ARINC bits match the control word program bits or if
the receiver decoder is disabled, then EOS clocks the data ready
flag flip flop to a "1",
flag for a receiver will remain low until after
that receiver are retrieved. This is accomplished by activating
with byte selector SEL low to retrieve the first byte and activating
EN
from receiver 1 and
If another ARINC word is received and a new EOS occurs before
the two bytes are retrieved, the data is overwritten by the new
word.
DATA
START
with SEL high to retrieve the second byte.
3. To validate the receive data bit rate, each bit must follow
its preceding bit by not less than 8 samples and not more
than 12 samples. With exactly 1MHz input clock frequency,
the acceptable data bit rates are
4. Following the last data bit of a valid reception, the Word
Gap timer samples the Null shift register every 10 input
clocks (every 80 clocks for low speed). If a Null is present,
the Word Gap counter is incremented. A Word Gap count of
3 enables the next reception.
CONTROL
BIT BD14
DATA BIT RATE MAX
DATA BIT RATE MIN
PARITY
CHECK
WORD GAP
SEQUENCE
DETECTION
CONTROL
ERROR
TIMER
32ND
BIT
EN2
D/R1
EOS
END
ERROR
CLOCK
SEQUENCE
COUNTER
retrieves data from receiver 2.
BIT CLOCK
END OF
OPTION
CLOCK
AND
BIT
or
D/R2
HIGH SPEED
125K BPS
(or both) will go low. The data
83K BPS
CLOCK
both
EN1
ARINC bytes from
CLK
LOW SPEED
10.4K BPS
15.6K BPS
retrieves data
EN