xrd9836 Exar Corporation, xrd9836 Datasheet

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... JUNE 2003 GENERAL DESCRIPTION The XRD9836 is a precision 16-bit analog front-end (AFE) for use in 3-channel/1-channel CCD/CIS docu- ment imaging applications. Pixel-by-pixel gain and offset for each of the 3 channels are controlled using a time multiplexed parallel input. Offset and Gain are sequentially supplied for red, green, and blue ...

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... XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0 IGURE THE EVICE P N ART UMBER XRD9836ACG ADCLK 1 48 Dgnd VSAMP 2 47 Dvdd BSAMP 3 46 OGI [0] LCLMP 4 45 OGI [ OGI [2] SCLK 6 43 OGI [3] SDIO 7 42 OGI [4] LOAD 8 41 OGI [5] Ovdd ...

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... OFFSET AND GAIN PARALLEL IN 4 digital in OFFSET AND GAIN PARALLEL IN 3 digital in OFFSET AND GAIN PARALLEL IN 2 digital in OFFSET AND GAIN PARALLEL IN 1 digital in OFFSET AND GAIN PARALLEL IN 0 (LSB) power Digital VDD ground Digital Ground 3 XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 D ESCRIPTION ...

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... XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 ELECTRICAL CHARACTERISTICS - XRD9836 Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz ARAMETER YMBOL Resolution R Fc3 Conversion Rate Fc1 Differential Non- DNL Linearity Input Referred ZSE Offset Offset Drift ZSD Input Referred FSE Gain Error Gain Error Drift ...

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... ELECTRICAL CHARACTERISTICS - XRD9836 (con’t) Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz ARAMETER YMBOL Input Voltage Range INVSR Input Leakage Iin Current Input Switch On Ron Resistance Input Switch Roff Off Resistance Internal Voltage Clamp CDS Vclampccd Input (inverting) Internal Voltage ...

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... XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 ELECTRICAL CHARACTERISTICS - XRD9836 (con’t) Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz ARAMETER YMBOL Gain Range Min. GRAN (Absolute Value) MIN Gain Range Max GRAN (Absolute Value) MAX Gain Resolution GRES P S ARAMETER YMBOL SYSTEM SPECIFICATIONS (I ...

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... ELECTRICAL CHARACTERISTICS - XRD9836 (con’t) Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz ARAMETER YMBOL ADCLK tadclk3 Duty Cycle tadclk1 ADCLK period tcp1 (1-Ch mode) ADCLK period tcp3 (3-Ch mode) Single Channel tcr1 Conversion period Three Channel tcr3 Conversion period BSAMP tpwb Pulse Width ...

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... XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 ELECTRICAL CHARACTERISTICS - XRD9836 (con’t) Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz ARAMETER YMBOL uSIO Data Setup Tuss Time uSIO Data Hold Time Tush uSIO Load Setup Tusls Time uSIO Load Tuslh Hold Time uSIO Period ...

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... ELECTRICAL CHARACTERISTICS - XRD9836 (con’t) Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz ARAMETER YMBOL Analog IDD I AVDD Digital IDD I DVDD Output IDD I OVDD IDD Total I DD Power Dissipation P DISS P S ARAMETER YMBOL Analog IDD I AVDD Digital IDD I DVDD Output IDD ...

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... Figure 5 A three-pin, Micro-controller Serial I/O link (uSIO) is used to write or read from the XRD9836’s internal configuration registers. The internal registers control the various modes of operation of the chip. ...

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... GAIN SELECT: The XRD9836’s Gain range is selectable to either with the Gain Select Bit. If Gain selected (Gain Select bit = 0), the maximum in- put is 1.0V. If Gain selected (Gain Select bit = 1), the maximum input is 0.5V. PARALLEL PORT FOR PIXEL OFFSET ...

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... LCLMP TIMING: In order to reject higher frequency power supply noise which is not attenuated near the sampling fre- quency, the XRD9836 utilizes a fully differential input structure. Since the CDS process uses AC coupled inputs, the coupling capacitor must be charged to the common-mode range of the analog front-end. This ...

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... IGURE AVEFORM EFINITION OF TERMS 3-CHANNEL CIS AND S/H MODE The XRD9836 also supports operation for Contact Image Sensor (CIS) and S/H applications. The red channel is synchronized on the rising edge of the first ADCLK after the sampling edge of VSAMP. In this mode of operation, the BSAMP input is con- nected to DGND, and input sampling occurs on the falling edge of VSAMP(VSAMP_POL=0) ...

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... XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 TIMING - CLOCK BASICS: The XRD9836 has 4 clock signals BSAMP, VSAMP, ADCLK and LCLMP. These inputs control the sam- pling, clamping and synchronization functions of the device. The pixel rate clocks are BSAMP, VSAMP and AD- CLK. BSAMP controls the sampling of the black refer- ence level of a CCD input signal ...

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... DelayD[3:0] DelayD[3:0] Tadcdo DelayA[3: UTPUT ATA ELAY DJUSTMENT Pixel (n-1) t PIX Black Sample Point Video Sample Point Offset (n) Gain (n+1) Offset (n+1) OGI Gain Togis Togih Sample Point DelayD[7:4] DelayD[7:4] DelayA[7:4] DelayA[7:4] 15 XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 Pixel (n) OGI Offset Sample Point ...

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... In some applications, alternate pixels along a scan line come from two different rows of CCD’s, causing a systematic offset between alternate pixels. When the XRD9836 is operated in the Fixed Gain Offset Mode (FGOM), it does not have the ability to compensate for this alternating offset phenomenon. ...

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... Note that SDIO is a bidirectional pin used to read or write the XRD9836 internal regis- ters. The R/W bit will define the direction of the bus after Address bits write to the XRD9836 is performed read of the XRD9836’s in- ternal registers is performed. ...

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... XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 ADDRESS RED RPGA [9] PGA GREEN GPGA [9] PGA BPGA BLUE [9] PGA RED DYNAMIC RDOFF [9] OFFSET GREEN GDOFF [9] DYNAMIC OFFSET BLUE DYNAMIC ...

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... BPGA BPGA BPGA BPGA [7] [6] [5] [ RDOFF RDOFF RDOFF RDOFF [7] [6] [5] [ XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0 RPGA RPGA RPGA RPGA [3] [2] [1] [ GPGA GPGA GPGA GPGA [3] [2] ...

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... XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 Green Dynamic D9 D8 Offset Register GDOFF GDOFF GDOFF [9] [8] (00100) default 0 1 GDOFF[9:0] sets the course offset level prior to the PGA of the Green channel. Code = 0000000000 is -80mV. Code =1111111111 is +160mV. Default is Code 0101010101 = 0 mV. Blue Dynamic ...

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... AGDOF AGDOF AGDOF AGDOF [7] [6] [5] [ ABDOF ABDOF ABDOF ABDOF [7] [6] [5] [ XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0 BFOFF BFOFF BFOFF BFOFF [3] [2] [1] [ ARDOF ARDOF ARDOF ARDOF [3] [2] ...

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... XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 APOAM Red Fine D9 Offset Register ARFOF ARFOF [9] (01100) default 1 RFOFF[9:0] sets the fine offset level after the PGA of the Red channel for even pixels in APOAM Mode. The offset is adjusted in 1mV increments. Code = 0000000000 is -128mV. Code =1111111111 is +128mV. Default is Code 1000000000 = 0 mV ...

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... PWRDWN - Puts the XRD9836 into power down state. PWRDWN = 0, normal operation. PWRDWN = 1, low power state. OEB - Enables the ADCDO bus. OEB = 0, data valid on ADCDO bus. OEB = 1, ADCDO bus high impedance. RESET - Will reset the XRD9836 to default (power up) conditions. RESET = 0, normal operation. RESET = 1, all inter- nal registers set to default values and clears itself after ~ 10ns. D7 ...

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... XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 Delay D9 Registers DelayA (10000) default DelayB (10001) default DelayC (10010) default DelayD (10011) default DelayA[7:4] - Controls the OGI_DLY. These bits are used to program the timing delay of the ADCLK used to sample the Offset-Gain-Inputs (OGI). Code 0000 is delay of 0ns, and code 1111 is 15ns. Default is 1000 = 7 ns. OGI_DLY should be larger than VSAMP_OGI_DLY ...

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... Test register used for factory test only. Do not modify NOFS2 TEST GAIN CCD/CIS ENABLE SELECT XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0 CHAN CHAN APOAM GOM [1] [ ...

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... TIMING DIAGRAMS CCDIN LCLMP ADCLK BSAMP VSAMP Clamp (Internal to XRD9836) F 17. 3-C IGURE HANNEL tap CCDIN LCLMP ADCLK tvfcr BSAMP tstl VSAMP Clamp (Internal to XRD9836) F 18. 1-C CDS M IGURE HANNEL tap tap X X tcp3 taclk3 taclk3 tvfcr tpwv tstl tbvf tcr3 CDS ...

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... CIS M IGURE HANNEL ODE tap CIS ADCCLK tstl VSAMP tpwv F 20. 1-C CIS M IGURE HANNEL ODE tcp3 tvfcr taclk3 taclk3 tcr3 ( CCD/CIS LL OLARITY BITS tcp1 taclk1 tcr1 ( CCD/CIS LL OLARITY BITS 27 XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0 BIT taclk1 tvfcr = 1) BIT ...

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... XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 Pixel (n) GAIN & OFFSET OGI 10bit parallel IE Tev Pixel (n-1) CCDOUT (Parallel RGB) BSAMP VSAMP Tva ADCLK ADC Samples Red ...

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... CCD A IGURE YPICAL PPLICATION The XRD9836 has an input range limitation of 1V maximum for a CCD input. If the maximum CCD out- put signal swing is greater than 1V, a resisitive divider network on the inputs can be used to reduce the CCD output to meet the 1V input max requirement of the XRD9836 inputs ...

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... XRD9836 16-BIT PIXEL GAIN AFE REV. 1.0.0 115 VDD = 3. 30MHz 3-Channel Mode 105 25. XRD9836 T IDD IGURE YPICAL 2 1.5 1 0.5 0 -0.5 -1 -1.5 0 8192 F 26. T XRD9836 DNL IGURE YPICAL Supply Current vs. Temperature Temperature( EMPERTURE 9836 System DNL 16384 24576 32768 ...

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... PACKAGE DRAWING: 16-BIT PIXEL GAIN AFE 31 XRD9836 REV. 1.0.0 ...

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... XRD9836 1.0.0 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no represen- tation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...