trcv012g5 ETC-unknow, trcv012g5 Datasheet - Page 15

• Manufacturer Part Number: trcv012g5
• Description: Trcv012g5 Gbits/s Trcv012g7 Gbits/s Gbits/s Limiting Amplifier, Clock Recovery, Data Demultiplexer
• Manufacturer: ETC-unknow

Preliminary Data Sheet
August 2000
Decision Circuit—Adjustable Sampling Time (ASTREF, AST[4:0])
The adjustable sampling time (AST) feature allows a deliberate time offset to be introduced for the data recovery
sampling instant relative to the recovered clock. The sampling instant is normally set by the clock recovery phase-
locked loop (PLL) to be midway between the mean values of adjacent NRZ data polarity transitions, which pro-
vides an ideal setup and hold time margin of one half the data period. By setting the AST[4:0] control bits, the user
may shift the instant at which the PLL’s recovered clock samples the receive data eye. The AST[4] bit acts as a
polarity setting, AST[3] represents the most significant magnitude bit, and AST[0] represents the least significant
magnitude bit. Since this results in two decoded zero time offset states, AST[4:0] = 00000 is used to disable the
sampling offset feature entirely and will result in traditionally defined midpoint sampling, whereas AST[4:0] = 10000
will also result in midpoint sampling by using the AST feature in its zero time offset condition. With AST[4] set to a
logic high, increasing the AST[3:0] hexadecimal code causes the sampling point to monotonically advance in time;
with AST[4] set to a logic low, the sample time is delayed more as AST[3:0] increases. The ASTREF pin should be
tied to the positive power supply through a low-capacitance 1%, 2.1 k
resistor to the AST circuitry
The AST control bit configurations and corresponding offset times are shown in Table 7
Table 7. Adjustable Sampling Time (AST) Control Code
Note: When operating the TRCV012G7 at the FEC rate, the 6.25 ps
Lucent Technologies Inc.
AST[4:0]
01101
01100
01011
01010
01001
01000
00110
00101
00100
00011
00010
00001
00000
01110
00111
01111
step should be scaled down by 7%.
Time Offset
–93.75
–87.50
–81.25
–75.00
–68.75
–62.50
–56.25
–50.00
–43.75
–37.50
–31.25
–25.00
–18.75
–12.50
–6.25
(ps)
0.00
.
AST[4:0]
Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
10000
10001
10010
10011
10100
10101
10110
11000
11001
11010
10111
11011
11100
11101
11110
11111
Time Offset
12.50
18.75
25.00
31.25
37.50
43.75
50.00
56.25
62.50
68.75
75.00
81.25
87.50
93.75
(ps)
0.00
6.25
resistor. This provides a stable reference
TRCV012G5 and TRCV012G7
.
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