uaa3580 NXP Semiconductors, uaa3580 Datasheet - Page 7

• Manufacturer Part Number: uaa3580
• Description: Wideband Code Division Multiple Access Frequency Division Duplex Zero If Receiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
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The receiver consists of an RF receiver front-end, an
RF VCO, a channel filter, Automatic Gain Control (AGC),
a RF fractional-N synthesizer PLL, a clock PLL, a
Power-up reset circuit and a 3-wire serial programming
bus.
8.1
The front-end receiver converts the aerial RF signal from
WCMDA (2.11 to 2.17 GHz) band down to a Zero
Intermediate Frequency (ZIF). The first stage is a
differential low noise amplifier matched to 50
external balun. The LNA is followed by an IQ down-mixer
which consists of two mixers in parallel but driven by
quadrature out-of-phase LO signals. The In phase (I) and
Quadrature phase (Q) ZIF signals are then low-pass
filtered, to provide protection from high frequency offset
interference, and fed into the channel filter.
8.2
The front-end zero IF I and Q outputs are applied to the
integrated low-pass channel filter with a provision for
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2002 Oct 30
self-calibrated fifth-order low-pass filter with a cut-off
frequency around 2.4 MHz. Once filtered the zero IF
I and Q outputs are further amplified with provision for
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output buffer provides close rail-to-rail output signal.
8.3
The RF VCO is fully integrated and self-calibrated on
manufacturing tolerances. It consists of 16 different
frequency ranges that are selected internally, depending
on the frequency programmation. It covers the necessary
bandwidth of 4.22 to 4.34 GHz and is tuned via the RF
charge pump and external loop filter. An internal supply
voltage regulator using the pin CAPVCOREG as external
decoupling capacitor supplies the RF VCO and minimizes
parasitic coupling and pushing. The regulator and the RF
VCO are turned on by the RXCEN signal.
8.4
The RF LO section covering the 4.22 to 4.34 GHz band is
driven by the internal RF VCO module. It includes the LO
buffering for the RF PLL and a divide-by-two circuit to
generate the quadrature LO signals to drive the RX IQ
down-mixer.
Wideband code division multiple access
frequency division duplex zero IF receiver
8 dB gain steps in front of the filter. The filter is a
FUNCTIONAL DESCRIPTION
1 dB steps and DC offset compensation. The zero IF
RF receiver front-end and RF VCO
Channel filter and AGC
RF VCO
RF LO section
using an
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8.5
A high performance RF fractional-N synthesizer PLL is
included on-chip which enables the frequency of the RF
VCO to be synthesized. The frequency is set via the 3-wire
serial programming bus.
The PLL is based on Sigma-Delta (
synthesis that enables the required channel frequency,
including Automatic Frequency Control (AFC) from a free
running external 26 MHz GSM reference frequency, to be
obtained. Very low close in-phase noise is achieved which
allows a wider PLL loop bandwidth and a shorter settling
time. The programmable main dividers are controlled by a
second-order (
VCO signals down to frequencies of 26 MHz (in
programmable 12 Hz steps). Their phase is then
compared in a digital Phase/Frequency Detector (PFD) to
the 26 MHz reference clock signal. The phase error
information is fed back to the RF VCO via the charge pump
circuit that ‘sources’ into or ‘sinks’ current from the loop
filter capacitor, thus changing the VCO frequency so that
the loop is finally brought into phase-lock.
The RF synthesizer division range enables an external
reference frequency of 13 to 26 MHz to be used.
8.6
The clock PLL is based on SD fractional-N synthesis that
allows the UMTS system clock, including AFC from a
non-corrected external 26 MHz GSM reference frequency,
to be obtained. The PLL comprises a fully integrated RC
VCO. The PLL output is a low harmonic content waveform,
the frequency of which can be programmed to
15.36, 30.72 or 61.44 MHz. The default value is
30.72 MHz.
8.7
The control of the chip is done via the 3-wire serial bus and
pin RXCEN. At power-up the clock PLL section is
automatically enabled, the other sections are enabled
when the RXCEN signal is set HIGH (also via the 3-wire
bus). The power-up signal is detected on pin V
the voltage rises. The V
maintained, enables the programming parameters to be
retained in memory.
RF fractional-N synthesizer PLL
Clock PLL
Control
) modulus controller. They divide the RF
DDD
pin, if the supply voltage is
Objective specification
) fractional-N
UAA3580
DDD
when