am85c30 Advanced Micro Devices, am85c30 Datasheet - Page 16

• Manufacturer Part Number: am85c30
• Description: Enhanced Serial Communications Controller
• Manufacturer: Advanced Micro Devices

I/O Interface Capabilities
The ESCC offers the choice of Polling, Interrupt (vec-
tored or nonvectored), and Block Transfer modes to
transfer data, status, and control information to and from
the CPU. The Block Transfer mode can be implemented
under CPU or DMA control.
Polling
All interrupts are disabled. Three status registers in the
ESCC are automatically updated whenever any func-
tion is performed. For example, end-of-frame in SDLC
mode sets a bit in one of these status registers. The idea
behind polling is for the CPU to periodically read a status
register until the register contents indicate the need for
data to be transferred. Only one register needs to be
read; depending on its contents, the CPU either writes
data, reads data, or continues. Two bits in the register
indicate the need for data transfer. An alternative is a
poll of the Interrupt Pending register to determine the
source of an interrupt. The status for both channels re-
sides in one register.
Interrupts
When an ESCC responds to an Interrupt Acknowledge
signal (INTACK) from the CPU, an interrupt vector may
be placed on the data bus. This vector is written in WR2
and may be read in RR2A or RR2B (Figures 8 and 9).
To speed interrupt response time, the ESCC can modify
3 bits in this vector to indicate status. If the vector is read
in Channel A, status is never included; if it is read in
Channel B, status is always included.
Each of the six sources of interrupts in the ESCC (Trans-
mit, Receive, and External/Status interrupts in both
channels) has 3 bits associated with the interrupt
source: Interrupt Pending (IP), Interrupt Under Service
(IUS), and Interrupt Enable (IE). Operation of the IE bit is
straightforward. If the IE bit is set for a given interrupt
source, then that source can request interrupts. The ex-
ception is when the MIE (Master Interrupt Enable) bit in
WR9 is reset and no interrupts may be requested. The
IE bits are write-only.
16
AD
INTACK
D
AMD
7
–AD
7
–D
INT
0
0
+5 V
IEI AD
7
–AD
Peripheral
0
INT INTACK IEO
Figure 7. Z-Bus Interrupt Schedule
Am85C30
IEI AD
The other 2 bits are related to the Z-Bus interrupt priority
chain (Figure 7). As a Z-Bus peripheral, the ESCC may
request an interrupt only when no higher priority device
is requesting one, for example, when IEI is High. If the
device in question requests an interrupt, it pulls down
INT. The CPU then responds with INTACK, and the in-
terrupting device places the vector on the A/D bus.
In the SCC, the IP bit signals a need for interrupt servic-
ing. When an IP bit is set to 1 and the IEI input is High,
the INT output is pulled Low, requesting an interrupt. In
the ESCC, if the IE bit is set for an interrupt, then the IP
for that source can never be set. The IP bits are readable
in RR3A.
The IUS bits signal that an interrupt request is being
serviced. If an IUS is set, all interrupt sources of lower
priority in the ESCC and external to the ESCC are pre-
vented from requesting interrupts. The internal interrupt
sources are inhibited by the state of the internal daisy
chain, while lower priority devices are inhibited by the
IEO output of the ESCC being pulled Low and propa-
gated to subsequent peripherals. An IUS bit is set during
an Interrupt Acknowledge cycle if there are no higher
priority devices requesting interrupts.
There are three types of interrupts: Transmit, Receive,
and External/Status. Each interrupt type is enabled un-
der program control with Channel A having higher prior-
ity than Channel B, and with Receive, Transmit, and
External/Status interrupts prioritized in that order within
each channel. When the Transmit interrupt is enabled,
the CPU is interrupted when the transmit buffer be-
comes empty. (This implies that the transmitter must
have had a data character written into it so that it can be-
come empty.) When enabled, the Receive can interrupt
the CPU in one of three ways:
7
–AD
Interrupt on First Receive Character or Special
Receive condition
Interrupt on all Receive Characters or Special
Receive condition
Interrupt on Special Receive condition only
Peripheral
0
INT INTACK IEO
IEI AD
7
–AD
Peripheral
0
INT INTACK
10216F-11
+5 V