am85c30 Advanced Micro Devices, am85c30 Datasheet - Page 25

• Manufacturer Part Number: am85c30
• Description: Enhanced Serial Communications Controller
• Manufacturer: Advanced Micro Devices

FIFO
FIFO Enhancements
When used with a DMA controller, the Am85C30 Frame
Status FIFO enhancement maximizes the ESCC’s abil-
ity to receive high-speed back-to-back SDLC messages
while minimizing frame overruns due to CPU latencies
in responding to interrupts.
Additional logic was added to the industry-standard
NMOS SCC consisting of a 10-deep by 19-bit status
FIFO, a 14-bit receive byte counter, and control logic as
shown in Figure 13. The 10 19 bit status FIFO is sepa-
rate from the existing 3-byte receive data and error
FIFOs.
When the enhancement is enabled, the status in Read
Register 1 (RR1) and byte count for the SDLC frame will
be stored in the 10
the DMA controller to transfer the next frame into
In SDLC mode, the following definitions apply:
2 Bits
All Sent bypasses MUX and equals contents of SCC Status Register.
Parity bits bypass MUX and do the same.
EOF is set to 1 whenever reading from the FIFO.
RR1
Interface to SCC
19 bit status FIFO. This allows
6-Bit MUX
Residue Bits(3)
Overrun
CRC Error
SCC Status Reg
(Existing)
6 Bits
RR1
5 Bits
Figure 13. SCC Status Register Modifications
10
EOF = 1
6 Bits
19 Bit FIFO Array
Bit 7
FIFO Overflow Status Bit
MSB of RR(7) is Set on Status FIFO
Overflow
FIFO Data Available Status Bit
Status Bit Set to 1
When Reading From FIFO
Bit 6
14-Bit Byte Counter
Am85C30
Bits 0–5
RR7
6 Bits
Byte Counter Contains 14 Bits
for a 16-kb Maximum Count
memory while the CPU verifies that the message was
properly received.
Summarizing the operation, data is received, assem-
bled, and loaded into the 3-byte receive FIFO before be-
ing transferred to memory by the DMA controller. When
a flag is received at the end of an SDLC frame, the frame
byte count from the 14-bit counter and 5 status bits are
loaded into the status FIFO for verification by the CPU.
The CRC checker is automatically reset in preparation
for the next frame, which can begin immediately. Since
the byte count and status are saved for each frame, the
message integrity can be verified at a later time. Status
information for up to 10 frames can be stored before a
status FIFO overrun could occur.
If receive interrupts are enabled while the 10 19 FIFO
is enabled, an SDLC end-of-frame special condition will
14 Bits
8 Bits
RR6
EN
End-of-Frame Signal
Status Read Comp
Head Pointer
4-Bit Counter
Tail Pointer
Comparator
Over Equal
Reset on Flag Detect
Increment on Byte DET
Enable Count in SDLC
Counter
4-Bit
4-Bit
FIFO Enable
WR(15) Bit 2 Set
Enables Status FIFO
10216F-17
AMD
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