scn2651 NXP Semiconductors, scn2651 Datasheet - Page 10

• Manufacturer Part Number: scn2651
• Description: Programmable Communications Interface Pci
• Manufacturer: NXP Semiconductors

Philips Semiconductors
character has been loaded into the holding register from the receive
shift register and is ready to be read by the CPU. If equal to zero,
there is no new character in the holding register. This bit is cleared
when the CPU reads the receive data holding register or when the
receiver is disabled by CR2. When set, the RxRDY output is low.
The TxEMT/DSCHG bit, SR2, when set, indicates either a change of
state of the DSR or DCD inputs or that the transmit shift register has
completed transmission of a character and no new character has
been loaded into the transmit data holding register. Note that in
synchronous mode this bit will be set even though the appropriate
“fill” character is transmitted. TxEMT will not go active until at least
one character has been transmitted. It is cleared by loading the
transmit data holding register. The DSCHG condition is enabled
when TxEN = 1 or RxEN = 1. If the status register is read twice and
SR2 = 1 while SR6 and SR7 remain unchanged, then a TxEMT
condition exists. It is cleared when the status register is read by the
CPU. When SR2 is set, the TxEMT/DSCHG output is low.
SR3, when set, indicates a received parity error when parity is
enabled by MR14. In synchronous transparent mode (MR16 = 1),
with parity disabled, it indicates that a character matching the DLE
register has been received. However, only the first DLE of two
successive DLEs will set SR3. This bit is cleared when the receiver
is disabled and by the reset error command, CR4.
1994 Apr 27
Programmable communications interface (PCI)
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The overrun error status bit, SR4, indicates that the previous
character loaded into the receive holding register was not read by
the CPU at the time a new received character was transferred into it.
This bit is cleared when the receiver is disabled and by the reset
error command, CR4.
In asynchronous mode, bit SR5 signifies that the received character
was not framed by the programmed number of stop bits. (If 1.5 stop
bits are programmed, only the first stop bit is checked.) If RHR = 0
when SR5 = 1, a break condition is present. In synchronous
non-transparent mode (MR16 = 0), it indicates receipt of the SYN1
character in single SYN mode or the SYN1 – SYN2 pair in double
SYN mode. In synchronous transparent mode (MR16 = 1), this bit is
set upon detection of the initial synchronizing characters (SYN1 or
SYN1 – SYN2) and, after synchronization has been achieved, when
a DLE–SYN1 pair is received. The bit is reset when the receiver is
disabled, when the reset error command is given in asynchronous
mode, and when the status register is read by the CPU in the
synchronous mode.
SR6 and SR7 reflect the conditions of the DCD and DSR inputs
respectively. A low input sets its corresponding status bit and a high
input clears it.
Product specification
SCN2651