scn2651 NXP Semiconductors, scn2651 Datasheet - Page 8

• Manufacturer Part Number: scn2651
• Description: Programmable Communications Interface Pci
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 5.
NOTE:
Baud rate factor in asynchronous applies only if external clock is selected. Factor is 16X if internal clock is selected. Mode must be selected
(MR11, MR10) in any case.
Table 6.
Table 7.
Command Register (CR)
Table 7 illustrates the command register. Bits CR0 (TxEN) and CR2
(RxEN) enable or disable the transmitter and receiver respectively.
A 0 to 1 transition of CR2 forces start bit search (async mode) or
hunt mode (sync mode) on the second RxC rising edge. Disabling
the receiver causes RxRDY to go high (inactive). If the transmitter
is disabled, it will complete the transmission of the character in the
transmit shift register (if any) prior to terminating operation. The TxD
output will then remain in the marking state (high) while TxRDY and
TxEMT will go high (inactive). If the receiver is disabled, it will
terminate operation immediately. Any character being assembled
will be neglected.
1994 Apr 27
00 = Normal operation
01 = Async: automatic
10 = Local Loopback
11 = Remote Loopback
Async: Stop bit length
00 = Invalid
01 = 1 Stop bit
10 = 1 1/2 Stop bits
11 = 2 Stop bits
Sync:
Number of SYN
char
0 = Double SYN
1 = Single SYN
Programmable communications interface (PCI)
MR27
CR7
echo mode
Sync: SYN and/or DLE
stripping mode
MR17
Operating Mode
Not used
Mode Register 1 (MR1)
Mode Register 2 (MR2)
Command Register (CR)
Sync:
Transparency
control
0 = Normal
1 = Transparent
CR6
MR26
MR16
0 = Force RTS
1 = Force RTS
0 = External
1 = Internal
Transmitter
Request
output high
output low
to Send
Parity Type
Clock
MR25
CR5
0 = Odd
1 = Even
MR15
0 = Normal
1 = Reset
0= External
1 = Internal
Reset Error
Parity Control
Receiver
0 = Disabled
1 = Enabled
error flag
in status reg
(FE, OE,
PE/DLE
DETECT)
MR24
Clock
CR4
MR14
8
Async:
Force Break
0 = Normal
1 = Force
break
Sync
Send DLE
0 = Normal
1 = Send DLE
Bits CR1 (DTR) and CR5 (RTS) control the DTR and RTS outputs.
Data at the outputs is the logical complement of the register data.
In asynchronous mode, setting CR3 will force and hold the TxD
output low (spacing condition) at the end of the current transmitted
character. Normal operation resumes when CR3 is cleared. The
TxD line will go high for at least one bit time before beginning
transmission of the next character in the transmit data holding
register. In synchronous mode, setting CR3 causes the
transmission of the DLE register contents prior to sending the
character in the transmit data holding register. CR3 should be reset
in response to the next TxRDY.
MR23
MR13
CR3
0000 = 50 Baud
0001 = 75
0010 = 110
0011 = 134.5
0100 = 150
0101 = 300
0110 = 600
0111 = 1200
Character Length
00 = 5 Bits
01 = 6 Bits
10 = 7 Bits
11 = 8 Bits
0 = Disable
1 = Enable
Receive
Control
MR22
(RxEN)
Baud Rate Selection
MR12
CR2
0 = Force DTR
1 = Force DTR
Data Terminal
1000 = 1800 Baud
1001 = 2000
1010 = 2400
1011 = 3600
1100 = 4800
1101 = 7200
1110 = 9600
1111 = 19,200
Mode and Baud Rate Factor
00 = Synchronous 1X rate
01 = Asynchronous 1X rate
10 = Asynchronous 16X rate
11 = Asynchronous 64X rate
output high
output low
MR21
Ready
MR11
CR1
Product specification
SCN2651
0 = Disable
1 = Enable
Transmit
Control
(TxEN)
MR20
MR10
CR0