hi-3717 QuickLogic Corp, hi-3717 Datasheet - Page 14

• Manufacturer Part Number: hi-3717
• Description: Single-rail Arinc 717 Protocol Ic With Spi Interface
• Manufacturer: QuickLogic Corp

FUNCTIONAL DESCRIPTION (cont.)
TRANSMITTER
FIFO Operation
The HI-3717 Transmit FIFO is loaded with ARINC 717 words
awaiting transmission. SPI words are written to the next Transmit
FIFO location with op-code 0x74 or 0x2 (Fast Write). If Transmit
FIFO Status Register empty flag, the TFEMPTY (TXFSTAT<5>) bit,
is “1” (FIFO empty), then up to 32 ARINC 717 12-bit words can be
safely loaded via the SPI interface. If the TFEMPTY bit is “0” then
less than 32 positions are available. If all 32 positions are filled,
then the full flag, the TFFULL (TXFSTAT<7>) bit, is “1”. All attempts
to load the Transmit FIFO are ignored until the TFFULL bit is “0”
which indicates that at least one word can be loaded.
The Transmit FIFO half-full flag, the TFHALF (TXFSTAT<6>) bit in
the Transmit FIFO Status Register, is equal to “0” when there are
less than or more than 16 ARINC 717 words in the Transmit FIFO
and equal to “1” when there are exactly 16 words in the FIFO. The
host CPU can safely load 16 ARINC 717 words into the Transmit
FIFO only when TFHALF is “1”.
The state of the TFFULL or TFHALF is available on the external
TFIFO pin, depending on the value in FSPIN<5> of the FIFO Status
Pin Assignment Register (See Table 7). The state of TFEMPTY flag
is always on the external TEMPTY pin.
It is the user’s responsibility to load the correct subframe sync mark
in the first word of each subframe and ensure the Transmit FIFO is
not left empty for more than one word time for continuous transmis-
sions.
The SPI format for writing an ARINC 717 word and Fast Word to the
HI-3717 Transmit FIFO is the same as the read format, except the
SCK
SO
CS
SI
LOAD SHIFT REGISTER
32 word x 12 bit FIFO
12 BIT PARALLEL
SPI INTERFACE
SPI COMMANDS
SPI COMMANDS
FIGURE 9.
ADDRESS
LOAD
HOLT INTEGRATED CIRCUITS
WORD CLOCK
ARINC 717 Transmitter Block Diagram
BIT CLOCK
HI-3717
ENCODER
ENCODER
BPRZ
CTRL0<6:4>
HBP
14
most significant bit of the op-code instruction is “0” rather than a “1”.
Data Transmission
The ARINC 717 transmission begins when the first word is loaded
into the Transmit FIFO. Each word is serially fed to both the HBP
and BPRZ encoders at the data rate programmed in Control
Register 0, CNTL0<6:4>. The output of each encoder drives its
own ARINC 717 analog line driver. The slew rate of both the HBP
and the BPRZ auxiliary outputs is controllable with CNTL0<2:1>.
Refer to the CTRL0 Register Description for the individual bit values
required for setting the desired data and output slew rate.
SYSTEM OPERATION
The receiver and transmitter always operate at the same data rate.
Otherwise, they operate completely independent of each other.
The only restrictions are:
DC/DC Converter
The HI-3717 requires only a single +3.3V power supply. An
integrated inverting / non-inverting voltage doubler generates the
rail voltages (±5.7V) which then power the line drivers to produce
the required +5V ARINC 717 HBP and ±5V ARINC 717 BPRZ signal
levels.
The internal dual-polarity charge pump requires four external
capacitors, two for each polarity generated by the charge pump.
CLOCK
DATA
1. The Receive FIFO ignores any attempt to load any additional
2. The Transmit FIFO can store a maximum of 32 words and
ignores any attempt to store additional words when it is full.
words if it is full and at least one location is not retrieved
before the next valid ARINC 717 is received.
SLEW RATE
LOOPBACK
CONTROL
WORD COUNTER
FIFO CONTROL
WORD CLOCK
DATA CLOCK
TEST
SEQUENCER
BIT CLOCK
&
LOADING
DIVIDER
FIFO
&
&
SEQUENCE
WORD COUNT
INCREMENT
START
LINE DRIVER
LINE DRIVER
BPRZ
HBP
TXHA
TXHB
TXOUTHA, OUTHA
TXOUTBA, OUTBA
TXBA
TXBB
TXOUTHB, OUTHB
TXOUTBB, OUTBB
ACLK
TFIFO
TEMPTY
NOCONV