s71ns128pc0 Meet Spansion Inc., s71ns128pc0 Datasheet - Page 5

• Manufacturer Part Number: s71ns128pc0
• Description: Burst Mode Multiplexed Flash Memory And Burst Mode Multiplexed Psram
• Manufacturer: Meet Spansion Inc.

1.1
2. Input/Output Descriptions
December 13, 2007 S71NS-P_00_05
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
Table 2.1
AMAX – A16
A/DQ15-A/DQ0
OE#
WE#
V
NC
F-RDY/R-WAIT
CLK
AVD#
F-RST#
F-WP#
F-ACC
R-CE#
F-CE#
R-CRE
F-VCC
SS
Base Ordering Part Number
Symbol
S71NS128PC0
S71NS256PC0
S71NS128PB0
S71NS256PB0
S71NS128PB0
S71NS128PC0
S71NS256PB0
S71NS256PC0
identifies the input and output package connections provided on the device.
D a t a
Address inputs
Multiplexed Address/Data
Output Enable input. Asynchronous relative to CLK for the Burst mode.
Write Enable input.
Ground
Ready output; indicates the status of the Burst read.
Flash Memory RDY (using default "Active HIGH" configuration)
V
V
Note: The default polarity for the pSRAM WAIT signal is opposite the default polarity of the
Flash RDY signal.
pSRAM WAIT (using default “Active HIGH” configuration)
V
V
To match polarities, change bit 10 of the pSRAM Bus Configuration Register to 0 (Active
LOW WAIT). Alternately, change bit 10 of the Flash Configuration Register to 0 (Active LOW
RDY)
Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK
increment the internal address counter. Should be at V
Address Valid input. Indicates to device that the valid address is present on the address
inputs.
Low = for asynchronous mode, indicates valid address; for burst mode, causes starting
address to be latched.
High = device ignores address inputs
Hardware write protect input. At V
outermost sectors. Should be at V
Accelerated input. At V
bypass mode. At V
conditions.
Chip-enable input for pSRAM.
Control Register Enable (pSRAM).
No Connect; not connected internally
Hardware reset input. Low = device resets and returns to reading array data
Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode.
Flash 1.8 Volt-only single power supply.
OL
OH
OL
OH
= data invalid
= data valid
= data valid
= data invalid
S h e e t
S71NS-P Memory Subsystem Solutions
Table 2.1 Input/Output Descriptions (Sheet 1 of 2)
IL
, disables all program and erase functions. Should be at V
HH
Package
( P r e l i m i n a r y )
, accelerates programming; automatically places device in unlock
ZJE
IL
IH
, disables program and erase functions in the four
for all other conditions.
Description
Model Number
TV
JR
IL
or V
IH
Packing Type
while in asynchronous mode
0, 3
IH
for all other
pSRAM Type
Type 3
Flash
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MCP Speed
66 MHz
83 MHz
RAM
X
X
X
X
X
X
X
X
X
X
X
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