s71jl064ha0bfw62 Advanced Micro Devices, s71jl064ha0bfw62 Datasheet - Page 37
s71jl064ha0bfw62
Manufacturer Part Number
s71jl064ha0bfw62
Description
Stacked Multi-chip Product Mcp Flash Memory And Psram Cmos 3.0volt-only, Simultaneous Operation Flash Memories And Static Ram/pseudo-static Ram
Manufacturer
Advanced Micro Devices
Datasheet
1.S71JL064HA0BFW62.pdf
(141 pages)
- Current page: 37 of 141
- Download datasheet (4Mb)
S29JL064H
For Multi-Chip Products (MCP)
64 Megabit (8 M x 8-Bit/4 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write
Flash Memory
Distinctive Characteristics
Architectural Advantages
Performance Characteristics
February 25, 2004 S71JLxxxHxx_00A1
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
— Zero latency between read and write operations
Flexible Bank architecture
— Read may occur in any of the three banks not being
— Four banks may be grouped by customer to achieve
Boot Sectors
— Top and bottom boot sectors in the same device
— Any combination of sectors can be erased
Manufactured on 130 nm process technology
SecSi™ (Secured Silicon) Sector: Extra 256 Byte
sector
— Factory locked and identifiable: 16 bytes available
— Customer lockable: One-time programmable only.
Zero Power Operation
— Sophisticated power management circuits reduce
Compatible with JEDEC standards
— Pinout and software compatible with single-power-
High performance
— Access time as fast as 55 ns
— Program time: 4 µs/word typical using accelerated
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
executing erase/program functions in another bank.
written or erased.
desired bank divisions.
for secure, random factory Electronic Serial
Number; verifiable as factory locked through
autoselect function.
Once locked, data cannot be changed
power consumed during inactive periods to nearly
zero.
supply flash standard
programming function
P r e l i m i n a r y
S29JL064H
Software Features
Hardware Features
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
Cycling Endurance: 1 million cycles per sector
typical
Data Retention: 20 years typical
Supports Common Flash Memory Interface (CFI)
Erase Suspend/Erase Resume
— Suspends erase operations to read data from, or
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
Unlock Bypass Program command
— Reduces overall programming time when issuing
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1,
— Acceleration (ACC) function accelerates program
Sector protection
— Hardware method to prevent any program or erase
— Temporary Sector Unprotect allows changing data in
program data to, a sector that is not being erased,
then resumes the erase operation.
program or erase cycles
multiple program command sequences
cycle completion
machine to the read mode
140, and 141, regardless of sector protect status
timing
operation within a sector
protected sectors in-system
37
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