s71jl064ha0bfw62 Advanced Micro Devices, s71jl064ha0bfw62 Datasheet - Page 43

• Manufacturer Part Number: s71jl064ha0bfw62
• Description: Stacked Multi-chip Product Mcp Flash Memory And Psram Cmos 3.0volt-only, Simultaneous Operation Flash Memories And Static Ram/pseudo-static Ram
• Manufacturer: Advanced Micro Devices

February 25, 2004 S71JLxxxHxx_00A1
Word/Byte Configuration
Requirements for Reading Array Data
Writing Commands/Command Sequences
The BYTE# pin controls whether the device data I/O pins operate in the byte or
word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only
data I/O pins DQ7–DQ0 are active and controlled by CE# and OE#. The data I/
O pins DQ14–DQ8 are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
To read array data from the outputs, the system must drive the CE# and OE#
pins to V
control and gates array data to the output pins. WE# should remain at V
BYTE# pin determines whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until the command register
contents are altered.
Refer to the AC
to
active current specification for reading array data.
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to V
For program operations, the BYTE# pin determines whether the device accepts
program data in bytes or words. Refer to “Word/Byte Configuration” for more
information.
The device features an Unlock Bypass mode to facilitate faster programming.
Once a bank enters the Unlock Bypass mode, only two write cycles are required
to program a word or byte, instead of four. The “Byte/Word Program Command
Sequence” section has details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 3
address” is the address bits required to uniquely select a sector. The “Command
Definitions” section has details on erasing a sector or the entire chip, or suspend-
ing/resuming the erase operation.
The device address space is divided into four banks. A “bank address” is the ad-
dress bits required to uniquely select a bank.
I
the write mode. The
bles and timing diagrams for write operations.
CC2
14
in the DC Characteristics table represents the active current specification for
for the timing diagram. I
indicates the address space that each sector occupies. Similarly, a “sector
IL
IL
. CE# is the power control and selects the device. OE# is the output
, and OE# to V
"Read-Only
P r e l i m i n a r y
"AC
Characteristics" section contains timing specification ta-
IH
Operations" section table for timing specifications and
.
CC1
in the DC Characteristics table represents the
S29JL064H
IH
. The
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